Arai, Y

Emura, T

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Development of a 24 ch TDC LSI for the ATLAS Muon DetectorYasuo Arai1 and Tsuneo Emura21KEK, National High Energy Accelerator Research Organization,Institute of Particle and Nuclear Studies, (yasuo.arai@kek.jp)2Tokyo University of Agriculture and TechnologyAbstractA prototype TDC LSI for the ATLAS precision muontracker (MDT) has been developed. The LSI wasprocessed in a 0.3 µm CMOS Gate-Array technology. Itcontains full functionality required in the final TDC.To get a high resolution around 300 ps, an asymmetricring oscillator and a PLL circuit are used. All the I/Osignals, which are active during measurement, haveLVDS interfaces. A JTAG interface is used for boundaryscan and internal register setup. All the memory andcontrol bits have parity bits so that a SEU can be detected.Radiation tolerance for Gamma ray and Neutron are alsoconfirmed.I.INTRODUCTIONATLAS precision muon tracker (MDT) requires high-resolution, low-power and radiation-tolerant TDC LSIs(called AMT: ATLAS Muon TDC). Total number ofTDC channels is about 370 kch.To study basic circuit elements and radiation tolerance,a test element group chip (AMT-TEG) was fabricated in1999 and reported in the last LEB workshop [1]. After thesuccess of the AMT-TEG chip, we have developed aprototype chip (AMT-1) which has full functionality forthe experiment. Here we report about the design and testresults of the AMT-1 chip. System tests with front-endchip, chamber and readout modules are being scheduled.AMT-1 chip was processed in a 0.3 µm CMOS Gate-Array technology (Toshiba TC220G). It contains 24 inputchannels, 256 words level 1 buffer, 8 words trigger FIFOand 64 words readout FIFO. It also includes trigger-matching circuit, which selects data according to thetrigger ID. The selected data are transferred through40~80 Mbps serial lines with DS-Link protocol.To get a high resolution and stable operation, anasymmetric ring oscillator and a Phase Locked Loop(PLL) circuit are used. All the input and output signalswhich are active during measurement has LVDSinterfaces. A JTAG interface is used for boundary scanand internal register setup. Built-In Self-Test formemories is also activated through the JTAG interface.All the memory and control bits have parity bits so that aSingle Event Upset can be detected.Although the technology is gate-array, we have madeintensive analog simulation and paid much attention tocell layout to achieve a sub-nano second timingresolution. Several macro cells are developed for timecritical and analog parts. Careful floor planning are doneto minimize route of the time critical signals.Photograph of the AMT-1 chips is shown in Fig. 1.The chip is packaged in a 144-pin plastic QFP with 0.5mm pin pitch and about 110k gates are used.Fig. 1 Photograph of the AMT-1 chip. The die size is about6 mm by 6 mm.II. MDT FRONT-END ELECTRONICSBlock diagram of the MDT front-end electronics isshown in Fig. 2. Three ASD (Amp-Shaper-Discri) chips[2] and one AMT chip are mounted on a small multi-layerprinted circuit board (mezzanine board), which plugs intoa MDT end plug PCB.Two modes of operation will be provided in MDTmeasurement. In one mode the ASD output gives the timeover threshold information, i.e. signal leading and trailingedge timing. The other mode measures leading edge timeand charge. The Wilkinson ADC serves as a time slewcorrection and also provides diagnostics for monitoringchamber gas gain. It operates by creating a gate of ~20nswidth at the leading edge of the signal, integrating chargeonto a holding capacitor during the gate, and then runningdown the hold capacitor at constant current (themaximum rundown time is of order 200ns). Thediscriminator also generates artificial dead time to avoidmultiple hits.Fig. 2 MDT front-end electronics. AMT chip receives timingsignal from three ASD chips and sends data to a ChamberService Module.III. AMT-1 CIRCUIT DESCRIPTIONBlock diagram of the AMT-1 chip is shown in Fig. 3,and main specification of the chip is summarized inTable. 1. Most of the circuits except time critical parts arewritten in Verilog code and logic synthesis are used.Since the detailed description of the chip is available inother documents [3, 4], only brief explanation ispresented here.Fig. 3 Block diagram of the AMT-1 chip.Table. 1 AMT-1 Specification (@40MHz System Clock)Least Time Count 0.78125 ns/bitTime Resolution 300 ps RMSDynamic range 13 (coarse) + 4 (fine) = 17 bitMax. Trigger Latency 16 bit (51 µsec)Int./Diff. Non Linearity < 80 ps RMSNo. of Channels 24 ChannelsLevel 1Buffer 256 wordsRead-out Buffer 64 wordsTrigger Buffer 8 wordsDouble Hit Resolution <10 nsHit Efficiency 100% @400 kHz(single edge)>99.8%@400kHz(two edge)Hit Input Level LVDSPower 3.3+-0.3V, ~500 mWProcess 0.3 µm CMOS Sea-of-GatePackage 144 pin plastic QFPA. Timing signalAccurate timing signals are derived from anasymmetric ring oscillator [5] which is stabilized with aPhase Locked Loop (PLL) circuit. The structure of theasymmetric ring oscillator (Fig. 4) is well fit to the gate-array structure and it generates even number of equallyseparated timing signals.The PLL produces a double frequency clock (80MHz) from a LHC beam clock (40MHz). By dividing the12.5 ns clock period into 16 intervals a time bin size of0.78 ns is obtained. Placement and route of this part isdone manually, and fine adjustments of load capacitanceare done for each output nodes.System clock for other parts are 40 MHz, and it isgenerated from the 80MHz clock. The entire system clocktree is automatically generated to reduce clock jitter.Fig. 4. (a) Schematics of an asymmetric ring oscillator (8 stages)and (b) timing diagram. Oscillator in the AMT-1 consists of16 stages.B. BuffersA hit signal is used to store the fine time and coarsetime measurement in individual channel buffers. The finetime measurement is obtained from taps along theasymmetric ring oscillator. The time of both leading andtrailing edge of the hit signal (or leading edge time andpulse width) can be stored. Each channel has a 4-wordbuffer where measurements are stored until they can bewritten into the common level 1 buffer.When a hit has been detected on a channel thecorresponding channel buffer is selected, the timemeasurement is encoded into binary form, the correctcoarse count value is selected and the complete timemeasurement is written into the L1 buffer together with achannel identifier.The L1 buffer is 256 hits deep and is written into likea circular buffer. Reading from the buffer is randomaccess such that the trigger matching can search for databelonging to the received triggers.C. Trigger matchingTrigger matching is performed as a time matchbetween a trigger time tag and the time measurementsthem selves. The trigger time tag is taken from the triggerFIFO and the time measurements are taken from the L1buffer. Hits matching the trigger are passed to the read-out FIFO. To prevent buffer overflow and to speed up thesearch time an automatic reject function can reject hitsolder than a specified limit when no triggers are waitingin the trigger FIFO.The trigger matching can optionally search a timewindow before the trigger for hits which may havemasked hits in the match window. A channel having a hitwithin the specified mask window will set its mask flag.The mask flags for all channels are in the end of thetrigger matching process written into the read-out FIFO ifone or more mask flags have been set.All data belonging to an event is written into the read-out FIFO with a header and a trailer (optional). Theheader contains an event id and a bunch id. The eventtrailer contains the same event id plus a word count.D. Control and status registersThere are two kinds of 12 bit registers, "Control" and"Status" registers. Contents of these registers are shownin Table. 2. The control registers are readable andwritable registers which control the chip functionality.The status registers are read only registers which showschip statuses.   Table. 2. Control (CSR0-15) and Status (CSR16-21) registers bit assignments.bit 11 10 9 8 7 6 5 4 3 2 1 0CSR0 global_reseterror_resetdisable_encodeenb_errrst_bcrevrtest_modetest_invertenb_directdisable_ringoscclkout_mode pll_multiCSR1 mask_windowCSR2 search_windowCSR3 match_windowCSR4 reject_count_offsetCSR5 event_count_offsetCSR6 bunch_count_offsetCSR7 coarse_time_offsetCSR8 count_roll_overCSR9 strobe_select readout_speed width_select - tdc_idCSR10 enb_auto_rejectnb_l1occup_radoutenb_matchenb_maskenb_relativeenb_serialenb_headerenb_trailerenb_rejectedenb_pair enb_trailingenb_leadingCSR11 enb_rofull_rejectenb_l1full_rejectenb_trfull_rejectenb_errmarkenb_mark_rejectednb_ermark_rejectedenb_errmark_ovrenb_l1ovr_detectenb_mreset_codeenb_resetcb_sepaenb_mreset_evrstenb_setcount_bcrstCSR12 enb_sepa_readoutenb_sepa_bcrstenb_sepa_evrstenb_errorCSR13 enb_channel[11:0]CSR14 enb_channel[23:12]CSR16 rfifo_emptyrfifo_fullcontrol_parityerrorCSR17 l1_emptyl1_nearly_fulll1_over_recoverl1_overflowl1_write_addressCSR18 tfifo_emptytfifo_nearly_fulltfifo_fullrunning l1_read_addressCSR19 coarse_countertfifo_occupancyl1_start_addressCSR20 coarse_counter[12:1]CSR21 0 0 0 0 0 0 rfifo_occupancy[5:0}There are 15 control registers and 6 status registers.These registers are accessible from 12-bit I/O bus orthrough JTAG interface. Since a SEU (Single EventUpset) in the control registers may cause important effecton the chip operation, a total parity of the control registersare stored in the status register. If a bit in the setupregister changes without normal write operation, a parityerror is caused and notified through an Error signal or anError packet.E. JTAG and BISTThe chip has JTAG boundary scan circuit, which isused to scan I/O pins, the control and status registers,internal circuit registers for debugging purpose, and BIST(Built-In Self-Test) for the level 1 buffer and FIFOs. Thechannel buffer and the level 1 buffer have a parity bit foreach word to detect SEU.IV. MEASUREMENT RESULTSThe chip was successfully operated and tested, thoughsome small bugs are found. Further systematic testscombined with the ASD, readout module, and a MDTchamber are scheduled in near future. Here some of thetest results are shown.A. PLLJitter of the ring oscillator was measured bymeasuring relative time distribution to input clock. Fig. 5-(a) shows the jitter dependence to the oscillatingfrequency. The jitter around operating point (80MHz) isless than 150 ps. This value is sufficiently low as for therequired resolution of 0.5 ns in the MDT.Fig. 5-(b) shows the jitter variation to the powersupply voltage (Vdd). This also shows good stabilityaround the operating point (3.3V).In the AMT-TEG chip [6], time jitter was about 140ps and time resolution of 305 ps was obtained in whichquantization error contributes 225ps. Both the DifferentialNon-Linearity (DNL) and Integral Non-Linearity (INL)were small (<80 ps RMS).There is no major change in the PLL and ringoscillator parts, so similar performance is also expected inthe AMT-1 chip.B. Serial ReadoutThe AMT-1 chip has a serial data interface in additionto a 32-bit parallel data interface. The serial interfacesupports both DS-protocol and simple data-clock output.The data transfer speed is selectable between 10 MHz to80 MHz, and 40 MHz will be used in the MDT.An example of waveform, which is driven by LVDSdrivers, is shown in Fig. 6. Packet of the data consists of astart bit, 32 bit data, a parity bit, and a stop bit.25020015010050σtp[ps]14012010080604020PLL Osc Freq [MHz]25020015010050σtp[ps]3.73.53.33.12.9Vdd[V](a)(b)Fig. 5 PLL jitter variation relative to input clock. (a) Frequencydependence (Vdd=3.3V), (b) Voltage dependence (PLL Osc =80 MHz).Fig. 6. LVDS serial output (DS protocol) wave form at 40Mbps.Upper lines show data line and bottom lines show strobe signal.C. Power ConsumptionTotal power consumption of the chip is measured atexpected operating condition and we observed about 500mW power dissipation. Most power consuming part isLVDS receiver at present design from the circuit analysis.Although the power consumption is marginal, furtherreduction of the power is planned by optimizing theLVDS receiver circuit.D. Radiation toleranceTotal dose expected for worst location of the MDTelectronics is 11 krad for 10 years LHC operation with asafety factor of 4. Radiation tolerance for gamma ray andneutron was measured in the AMT-TEG chip andreported in reference 1 and 6. Present CMOS processshows adequate radiation tolerance for use in MDTenvironment.Furthermore we also irradiated the AMT-1 chip togamma ray at Tokyo Metropolitan University with a Co60source. The irradiation rate was about 76 rad(Si)/sec, andtotal dose irradiated was 30 krad(Si). During theirradiation power and clock are supplied to the chip. Tostudy post-radiation effects, measurements were alsodone after annealing (1 week at room temperature and 1week at 100 degree C) following the "ATLAS Policy onRadiation Tolerant Electronics" procedure [7].We have measured variation of PLL oscillation andincrease of leakage current. There is no obvious changeobserved up to the 30 krad(Si) irradiation.V. SUMMARYA prototype TDC chip (AMT-1) was developed forATLAS MDT detector. The chip was fully functional andshowed adequate performance. After thorough system testwith other electronics and chambers, a production chipwill be designed with minor modifications to the presentchip. Mass production is scheduled around the end of year2001.ACKNOWLEDGEMENTSI would like to thank to O. Umeda, I. Sakai, K.Tsukamoto and T. Takada (Toshiba Co.) for theirtechnical support. I also thank to T. Kondo (KEK) for hiscontinuous encouragement.REFERENCES[1] Y. Arai, "Performance and Irradiation Tests of the 0.3µm CMOS TDC for the ATLAS MDT", Proceedingsof the Fifth Workshop on Electronics for LHCExperiments, Snowmass, 1999. CERN/LHCC/99-33,pp. 462-466.[2] John Huth, John Oliver, Werner Riegler, Eric Hazen,Christoph Posch, Jim Shank, " Development of anOctal CMOS ASD for the ATLAS Muon Detector",Proceedings of the Fifth Workshop on Electronics forLHC Experiments, Snowmass, 1999.CERN/LHCC/99-33, pp. 436-442.[3] Y. Arai and J. Christiansen, "TDC Architecture Studyfor the ATLAS Muon Tracker", Proceedings of theThird Workshop on Electronics for LHC Experiments,London, Sep. 1997. CERN/LHC/97-60, pp315-319.[4] http://atlas.kek.jp/~araiy/.[5] Y. Arai and M. Ikeno, “A Time Digitizer CMOSGate-Array with a 250 ps Time Resolution”, IEEEJournal of Solid-State Circuits, Vol. 31, No. 2, Feb.1996, pp. 212-220.[6] Y. Arai, "Development of Front-end Electronics andTDC LSI", Nucl. Instr. and Meth. A, Vol. 453, pp.365-371 (2000).[7] Atlas policy on radiation tolerant electronics.http://www.cern.ch/Atlas/GROUPS/FRONTEND/radhard.htm

Development of a 24 ch TDC LSI for the ATLAS muon detector

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