Gennari, E

Petrolo, E

Salamon, A

Vari, R

Veneziano, Stefano

CERN Document Server

Radiation Tolerance Evaluation of the ATLAS RPC Coincidence Matrix SubmicronTechnologyE.Gennari, E.Petrolo, A.Salamon, R.Vari, S.VenezianoINFN Sezione di Roma, P.le Aldo Moro 2, 00185 Roma, ItalyRiccardo.Vari@roma1.infn.itAbstractThe Coincidence Matrix ASIC is the central part of theATLAS level-1 muon trigger in the barrel region; it performsthe trigger algorithm and data read-out. The ASIC will bemounted on dedicated boards on the Resistive Plate Chamberdetectors. The chosen technology has to guarantee completefunctionality in the ATLAS RPC radiation environment.Radiation tests have to satisfy the radiation tolerance criteriaproposed by the ATLAS Policy on Radiation TolerantElectronics. The ATLAS standard test methods has to befollowed in order to guarantee both total dose and single eventeffects tolerance.A frequency multiplier ASIC was used for technologyevaluation and radiation tests. The chip is a low jitterprogrammable clock multiplier, realised in 0.25 µm CMOStechnology. This frequency multiplier is intended to be usedin the Coincidence Matrix ASIC as a macro, to perform theinternal clock frequency multiplication. Radiation test resultswill be presented.I. INTRODUCTIONThe Coincidence Matrix ASIC (CMA) performs theATLAS barrel level-1 muon trigger algorithm and ResistivePlate Chambers data read-out. ~4000 CMA will be mountedon dedicated boards on the RPC detectors. The CMA chipexecutes the timing and digital shaping of the signals comingfrom the RPC doublets, the high PT and low PT triggeralgorithm, the data storage during level-1 latency, the triggerand data read-out generation, the storage of read-out data inderandomizing memory and the serialisation of read-out data[1] [2]. Figure 1 shows the trigger algorithm basic scheme.The CMA is required to tag incoming hits with a timeresolution greater then the bunch crossing period, and has aninternal pipeline working at 320 MHz for this purpose. Aninternal clock multiplier is so required to perform frequencymultiplication of the external 40 MHz clock.The Fujitsu ULPM2 is a low jitter programmable clockmultiplier, realised in 0.25 µm CMOS technology with triplewell. A delay locked loop (DLL) provides the chip clockoutput, within a range between 40 MHz and 400 MHz. Themultiplying factor is programmable between 2 and 32. Powersupply is 2.5 V. The ULPM2 chip has been chosen as acandidate for the CMA internal clock multiplier, and it isintended to be used as a macro in the CMA chip, to performthe 8x40 MHz internal frequency multiplication.Figure 1: The high PT and low PT trigger schemeFujitsu released the macro for testing in a 120-pin QFPplastic package. The tests were intended to be useful forevaluating the Fujitsu technology, the radiation tolerance ofthe process, and the ULPM2 frequency multiplierfunctionality, so as to decide if the Fujitsu technology and theULPM2 could both be used for the CMA chip. In order to testradiation tolerance of this deep submicron process, tests wererepeated after gamma and proton irradiation. The technologyhas to guarantee complete functionality in the ATLAS RPCradiation environment.II. ULPM2 TESTA test board for the ULPM2 chip has been developed inRome INFN lab. The ULPM2 input clock can be connected toan external generator or to a on board oscillator. A fewswitches select the macro control signals and initialisationregisters. A special output signal is provided in the chip tomonitor the status of the ULPM2 DLL lock.A. Functionality testThe macro clock input has been connected to an externalpulse generator, in order to monitor the output clock as afunction of the input one. Clock functional range has beenfirst tested. The output clock working range, for all possiblemultiplying factors, has been verified. In order to monitor theDLL lock status, the ULPM2 lock signal has been connectedto a transformer/shaper and then to a pulse counter. The chiphas shown a correct functionality, in accord with the FujitsuULPM2 datasheet values [3]. Maximum measured outputclock jitter is 25 ps RMS, 170 ps P-P.In order to evaluate the frequency multiplier linearity,output clock has been monitored for different values of theinput clock, in steps of 2 MHz, for a fixed multiplicationfactor equal to 8. The measured integral and differential non-linearity is less then 6‰. ULPM2 output frequency standarddeviation has been measured. RMS output frequency standarddeviation is less then 5‰ the input frquency. No appreciabledifference has been observed between different tested chips.B. Total Ionising Dose testFor this test the ATLAS TID standard test method hasbeen followed [4]. Two chips have been tested. The ULPM2chip has been irradiated with a Cobalt 60 γ source. TheGammacell 220 High Dose Rate Research Irradiator has beenused (facility from Istituto Superiore di Sanità, Rome). Doserate during irradiation has been 481 Rad/minute.The ULPM2 chip has been irradiated up to a total dose of~300 kRad. Chip functionality, output clock jitter, frequencyand amplitude has remained unchanged during irradiation.Differential and integral non-linearity has been measured afterirradiation. Figure 2 and Figure 3 show differential andintegral non-linearity before and after irradiation. DNL andINL measured values has not changed appreciably afterirradiation. Power consumption has been monitored duringirradiation, showing a final increase of ~25%, as can be seenin Figure 4. Annealing measurements have been done, forsimulating low dose effects. Measurements were done duringten days at room temperature, and then during ten days at 80°C. During annealing, the macro showed a correctfunctionality. After ten days at room temperature, powerconsumption was still 14% more than the one beforeirradiation (see Figure 5). Then, after ten days at 80 °C, powerconsumption decreased down to 8% the original value (tenweeks at 80 °C are requested for coming back at originalvalues).The radiation tolerance criteria proposed in the ATLASTID test method for the RPC isRTCtid = SRLtid · SFsim · SFldr · SFlot · 10ywhere:SRLtid = 3.0 · 10-1 Gy/y (RPC worst location);SFsim = 3.5 (safety factor for simulation inaccuracies);SFldr = 1 (safety factor for low dose rate effects);SFlot = 4 (safety factor for different lot);10y = ten years of LHC working operation.Using these values we obtain RTCtid = 4.2 kRad, which is~70 times less then the maximum total dose taken by the chipduring TID test. The calculated RTCtid clearly shows that TIDis not a problem in the RPC radiation environment.-1000-500050010000 5 10 15 20Input frequency stepDNL [kHz]Figure 2: Differential non-linearity before and after irradiation-2500-2000-1500-1000-500050010000 5 10 15 20Input frequency stepINL [kHz]Figure 3: Integral non-linearity before and after irradiation181920212223240 100 200 300 400Total dose [kRad]Power consumption [mW]Figure 4: ULPM2 power consumption during irradiation19.520.020.521.021.522.022.523.023.50 100 200 300 400 500 600Time of annealing [hours]Power consumption [mW]Figure 5: ULPM2 power consumption during annealingC. Single Event Effects testFor this kind of test the ATLAS SEE standard test methodwas followed.Irrad1 proton facility at CERN Proton Synchrotron (PS)was used. The proton beam forms a spot of (2x2) cm2, and hasan energy equal to 24 GeV. The proton flux at the centre ofthe beam is (2÷9) · 109 cm-2s-1. In order to have a reducedparticle flux on the electronics to be tested, it is possible toplace the test board outside the beam centre. In this case thetotal particle flux contribution comes from back-scatteringparticles and from the 24 GeV proton beam halo. Figure 6shows Irrad1 back-scattering energy spectrum (values fromFLUKA simulation). As can be seen from the histogram, theenergy of the back-scattered particles is high enough togenerate SEE in the irradiated chip.The ULPM2 chip has been placed 10 cm far from beamcentre, in order to have on the chip ~1% of the maximum fluxduring irradiation. With this reduced error rate a more easyerror monitor and control is possible. Total irradiation timehas been 6 hours, obtaining a total fluency on the ASIC equalto 1.38 · 1012 h/cm2 (1.68 · 1014 h/cm2 at beam centre). Nohard or destructive errors have been detected. Only soft SEUhave been detected, coming from ULPM2 DLL loss of lock.The DLL has been able to recover the lock within 4 clockperiods (100 ns), and so no reset has been necessary duringirradiation.  Figure 7 shows the measured error timedistribution histogram.Assuming that the effective cross-section for protons isconstant up to 24 GeV [5], the number of foreseen errors inthe ATLAS RPC radiation environment can be calculatedwith the following formula:soft SEUf = (soft SEUm / ARL) · (SRLsee / 5 · 107s) · SFsimwhere:• soft SEUf: foreseen rate of soft SEU in a given ATLASlocation [soft SEU/s];• soft SEUm: total number of soft SEU measured duringproton irradiation;• ARL: Applied Radiation Level (integrated flux of 60÷200MeV proton applied) [h/cm2];• SRLsee: integrated flux of hadrons with energy > 20 MeV in10 years [h/cm2];• 5 · 107s: integrated beam time expected in 10 years of LHCoperation;• SFsim: safety factor representing SRLsee inaccuracies.1.E-031.E-021.E-011.E+0013 33 53 73 93 113133153173193213233kinetic energy [MeV]arb. unitsFigure 6: Irrad1 proton back-scattering energy spectrum01230 30 60 90 120 150 180 210 240 270time [min]number of errorsFigure 7: Number of measured SEU during 280 min. of irradiationUsing the formula we obtain:soft SEUf = 5.6 · 10-8 soft SEU/s = 4.8 · 10-3  soft SEU/day.With this value we can calculate the foreseen dead timeinduced in the Coincidence Matrix ASIC by the ULPM2 softSEU errors. Assuming to perform a CMA reset every fixedreset period, we define CMA dead time as the time intervalbetween a soft SEU occur in the ULPM2 and the next CMAreset (see Figure 8). Assuming an exponential distribution forthe time between two soft errors, the induced CMA dead timewill be:TD = TR-1/λ·(1-e-λTR)where:TD = dead time;TR = trigger reset period;λ = soft SEU rate = 5.6 · 10-8 s-1.Figure 8: CMA dead timeWe are so able to calculate the CMA dead time percentageas a function of the reset time. Figure 9 shows that dead timepercentage values are acceptable for our purposes.0.E+001.E-062.E-063.E-064.E-065.E-066.E-067.E-068.E-069.E-060 50 100 150 200 250 300 350reset perion [s]Td/TrFigure 9: Dead time percentage vs. reset periodIII. CONCLUSIONSFujitsu technology evaluation, using the ULPM2 clockmultiplier has been successful.Total Ionising Dose test, following the ATLAS standardtest method, has shown that the 0.25 µm CMOS technology isradiation tolerant enough for our purposes. Powerconsumption increase, due to the total dose, in negligible forthe foreseen radiation values in the RPC region.Single Event Effect test has shown that this technology isnot sensitive to destructive SEE, such as Single EventLatchup or Single Event Burnout. Only soft SEU weredetected, coming from the ULPM2 DLL loss of lock. Thedead time introduced in the CMA from this kind of errors isacceptable. Anyway, in order to keep low the CMA error rate,redundancy to SEU will be introduced in the CMA maincontrol logic.IV. REFERENCES[1] E.Petrolo, A.Salamon, R.Vari, S.Veneziano, Barrel LVL1Muon Trigger Coincidence Matrix ASIC: User RequirementsDocument, ATL-COM-DAQ-2000-050.[2] ATLAS Level-1 Trigger Group, ATLAS Level-1 TriggerTechnical Design Report, August 1998, ATLAS TDR-12[3] Fujitsu Mikroelektronik GmbH, ULPM2 MacroDatasheet, June 1999.[4] M.Dentan, P.Fartouat, ATLAS Policy on RadiationTolerant Electronics, revision 2, July 2000[5] F.Faccio, M.Huhtinen, Computational method to estimateSingle Event Upset rates in an accelerator environment,October 1999, submitted to Elsevier PreprintTTR0 Tresetn TSEUtTresetn+1

Radiation tolerance evaluation of the ATLAS RPC coincidence matrix submicron technology

Abstract

Similar works

Full text

Available Versions

CERN Document Server