We present a 128-channel analogue front-end chip SCTA128 for readout of silicon strip detectors employed in the inner tracking detectors of LHC experiments. The architecture of the chip and critical design issues are discussed. The performance of the chip has been evaluated in detail in bench tests and is presented in the paper. The chip is used to read out prototype analogue modules compatible in size, functionality and performance with the ATLAS SCT base line modules. Several full size detector modules equipped with SCTA128 chips have been built and tested successfully in the lab with E particles as well as in beam tests

Chesi, Enrico Guido

Cindro, V

Clark, J A

Dabrowski, W

Ferrère, D

Kaplon, J

Kramberger, G

Lacasta, C

Lozano-Bahilo, J

Mikuz, M

Morone, C

Roe, S

Rudge, A

Szczygiel, R

Tadel, M

Weilhammer, Peter

Zsenei, A

Kaplon, J.

Chesi, E.

Clark, Allan Geoffrey

Cindro, V.

Dabrowski, W.

Ferrere, D.

Kramberger, G.

Lacasta, C.

Lozano, J.

Mikuz, M.

Morone, Maria Cristina

Roe, S.

Rudge, A.

Szczygiel, R.

Tadel, M.

Weilhammer, P.

Zsenei, Andras

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Analogue read-out chip for Si strip detector modules for LHC experiments

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Analogue Read-Out Chip for Si Strip Detector Modules for LHC ExperimentsKaplon J.1  (e-mail: Jan.Kaplon@cern.ch), Chesi E.1, Clark J.A.2, Cindro V.3, Dabrowski W.4,Ferrere D.2, Kramberger G.3, Lacasta C.5, Lozano J.1, Mikuz M.3, Morone C.2 Roe S.1, Rudge A.1,Szczygiel R.1, Tadel M.3, Weilhammer P.1, Zsenei A.21CERN, 1211 Geneva 23, Switzerland2University of Geneva, Switzerland3Jozef Stefan Institute, Ljubljana, Slovenia4Faculty of Physics and Nuclear Techniques, UMM, Krakow, Poland5IFIC, Valencia, SpainAbstractWe present a 128-channel analogue front-end chipSCTA128 for readout of silicon strip detectors employedin the inner tracking detectors of LHC experiments. Thearchitecture of the chip and critical design issues arediscussed. The performance of the chip has beenevaluated in detail in bench tests and is presented in thepaper. The chip is used to read out prototype analoguemodules compatible in size, functionality andperformance with the ATLAS SCT base line modules.Several full size detector modules equipped withSCTA128 chips have been built and tested successfully inthe lab with E particles as well as in beam tests.I. INTRODUCTIONThe LHC operating conditions present a greatchallenge to the front-end electronics of Si trackers forexperiments designed for high luminosity physics.Historically most collider experiments have so far usedfull analogue readout front-ends for Si trackers and vertexdetectors. This method allows individual treatment ofdata in each channel with optimised and adaptablesoftware and thereby the most detailed control andmonitoring of the whole system. Analogue readout is to alarge extent immune to external electromagnetic pickup(common mode) since common mode noise can be fullyeliminated with software. The price to pay for this safetyis a heavier load on data transmission from the detectorover optical links, both in bit rate and in the requirednumber and quality of the links.The ATLAS Semiconductor Tracker has adopted a binaryscheme for the readout of silicon strip detectors as thebaseline. The binary architecture allows a more compactdesign and has the advantage of a much reduced datatransfer rate with more chips using a single optical link.This architecture is, however, not immune at all tocommon mode noise and so is very sensitive to externalelectromagnetic interference.In this paper the ATLAS back-up solution, the SCTA128chip will be presented. The SCTA128 chip is an exampleof analogue readout architecture for silicon stripdetectors, which meets all basic requirements of the LHCexperiments. It comprises five basic blocks: front-endamplifiers, analogue pipeline (ADB), control logicincluding derandomizing FIFO, command decoder andoutput multiplexer. The chip has been manufactured inthe DMILL process, the same as used for the binary chipABCD [1], [2]. The front-end is a fast transimpedanceamplifier, using a bipolar input transistor and providingpulse shaping with peaking time of 25 ns.The design and the performance of the chip will bepresented. The basic chip performance has been evaluatedon a test bench. An analogue prototype module consistingof two 6.4 cm x 6.3 cm ATLAS baseline detectors readout by 6 SCT128A chips has been built. The chips aremounted on a ceramic hybrid connected to the sensors inan end-tap configuration. The pitch adapter needed tomatch the strip pitch of  80 Pm and the pitch of input padson the chip, which is 60 Pm, is integrated on the hybrid.The performance of the module, which has been testedwith a Ru E-source and in a 100 GeV pion beam, will bediscussed.II. CHIP ARCHITECTUREFigure 1 shows the block diagram of the SCTA128chip.Figure 1: Block diagram of the SCTA128 chip.The SCTA128 chip comprises the following buildingblocks: 128 channels with front-end amplifiers, AnalogueMemory (ADB) with the capacity to store 128 analoguesamples, control logic providing a derandomizingfunction (up to 8 events), command decoder and fastInput pads from the detectorFEADBanalogueMUXDAC’s& CALlogicADB controlReadoutlogicCommand decoderanalogue multiplexer to output serial data. In addition tothe basic functional blocks, internal calibration circuitrycontaining an 8-bit DAC to control the calibration levelhas been implemented to improve the testability of thechip.  Four 5-bit DAC’s for the bias of the analogue partof the chip have been implemented in order tocompensate the drifts after irradiation and optimise chipperformance for various parameters (noise level for agiven detector capacitance, required dynamic range etc.).The details of the chip architecture and basic principles aswell as readout protocol may be found in previouspublications [3], [4].III. RESULTS FROM THE PROTOTYPE CHIPSCTA128HC.In this section we briefly review results from theperformance of the prototype chip SCTA128HC alreadypresented in previous publications [3] and [4]. We presentalso the latest results obtained from beam tests of a fullsize (13cm length) ATLAS type detector modules.The SCTA128HC chip was manufactured in themiddle of 1998 – an early stage of DMILL stabilisationprocess at TEMIC. Looking at the noise figure obtainedwith this prototype chip it should be remembered that thetypical value of the BJT beta was in the range of 100(today 250) which obviously has an impact on the valueof parallel noise. In addition to that the SCTA128HC chipsuffers from two technological problems not fullyunderstood at the time of submission. One was thesusceptibility of the RHV type resistors (used in the front-end) to the radiation which makes a whole design non-rad-hard. The second one was the problem of the parasiticcoupling through the substrate of the chip (described in[5]) limiting the phase margin and causing an oscillation.The temporary solution cancelling that effect wasthinning and metallization of the chip backplane done inan extra process step outside the foundry.A. Basic chip performance – results from asingle chip evaluation board.Basic requirements for the front-end performance arethe speed, noise figure and the dynamic range. In theSCTA128HC chip there is no direct access to the outputof the FE amplifier however the pulse shape can beevaluated by scanning the delay of the calibration signalwith respect to the phase of the ADB sampling clock.Figure 2 shows the example of a delay scan normalised tothe absolute time scale for one particular front-endchannel. The injected charge was 6 fC. The obtained 25ns peaking time matched the design value well.Figure 3 shows the gain linearity for one particularchannel of the chip. The gain is in the range of 28 mV/fCand the linearity is kept up to 12fC, which is enough fortracking applications.The overall distribution of the gain in oneSCTA128HC chip is presented in figure 4. The RMSspread of the gains is about 3%, which is acceptable fortracking applications. The spread between the on-chipcalibration capacitors (100 fF in each channel) and thecalibration resistors (one for calibration line) alsocontributes to this distribution.10 20 30 40 50020406080100120140160180200220Channel 100[mV](calibration strobe delay) x 1.2 nsreal time direction25 nsFigure 2: Pulse shape at the multiplexer output obtained fromthe delay scan.Input charge [fC]0 2 4 6 8 10 12 14 16Output [mV]050100150200250300350400Chi2 / ndf = 0.4338 / 14OffSet   = -21.8 +- 1.797 Gain     = 28.29 +- 0.3578 SCTA128HC, single channelFigure 3: Gain linearity for a single channel of SCTA128HC.Gain [mV/fC]15 20 25 30 35 40 45Entries05101520253035GainNent = 128    Mean  =  28.04RMS   = 0.9621SCTA128HC GainFigure 4: Distribution of the front-end gain in one SCTA128HCchip.The noise measurements of the front-end have beenperformed for the whole chip running with a 40 MHzclock sampling data to the analogue memory and forrandom readout of the ADB cells.  This way any pedestalvariation between ADB cells was included in the overallnoise performance. Noise slopes for different values ofthe input transistor bias are shown in figure 5.Cinput [pF]0 2 4 6 8 10400600800100012001400ENC [e-]Ipre = 200uA ENC = 757 + 38e-/pFIpre = 160uA ENC = 707 + 43e-/pFIpre = 100uA ENC = 634 + 53e-/pFFigure 5: ENC noise slope for different bias conditions of theinput transistor.As already mentioned the ENC value for zero inputcapacitance is limited by relatively low beta (around 100)of BJT transistors manufactured at TEMIC in 1998.The spread of the pedestals in the analogue memoryhas a direct impact on the overall noise performance ofthe whole chip. Since the analogue memory performs asimple voltage sampling, the pedestal spread willcontribute, as an extra noise source uncorrelated with theinput noise. The distribution of the pedestals in the ADBfor a typical channel of the SCTA128HC is shown infigure 6.-154 -153 -152 -151 -150 -149 -148051015202530Chi2 / ndf = 6.01507 / 7Constant = 30.5428 Mean     = -151.055 Sigma    = 0.381177 ADB dispersion for channel 100Figure 6: Pedestal distribution of 128 cells in one typicalchannel of SCTA128HC chip readout with 40 MHz clock.The value of 0.4 mV has to be compared with 28 mV/fCgain, which gives additional noise contribution in therange of 100e- ENC uncorrelated with the input noise.The measurement has been done using 40 MHz readoutclock for the output multiplexer, which is synchronouswith the ADB sampling clock. Using slower multiplexerclock increase activity of the digital signals asynchronousto the sampling clock which couple through the chipsubstrate to the inputs of the front-end and increase thepedestal spread. The typical value of RMS pedestalsspread in analogue memory for lower readout frequencyis in the range of 1.2 mV.B. Performance of the ATLAS type detectormodules equipped with SCTA128HC chips.To demonstrate the feasibility of using the SCTA128chip as a backup solution for the ATLAS SCT severalmodules compatible with the size and number ofelectronic channels of the baseline binary module havebeen built. A 6 chip ceramic hybrid holding 2 silicondetectors of size 6.3x6.4 cm (ATLAS baseline design) inend-tap configuration is shown in figure 7.Figure 7: Photograph of a 13-cm module with 6 SCTA128HCchips.The modules were tested in the SPS beam line, whichprovides 100 GeV pions. A standard procedure describedin [4] was applied to extract spatial resolution, efficiencyand noise occupancy for the tested modules. The signalover noise distribution of the found clusters on 13-cmstrips regions is shown in figure 8. The most probablevalue is about 20, which is sufficient to provide highparticle detection efficiency while keeping the noiseoccupancy well below ATLAS requirements.20 40 60 80 100050100150200250300 Chi2 / ndf =  55.4 / 44Scale    = 1.283 +- 0.06274 Peak     = 19.99 +- 0.08305 Norm     =  3309 +- 60.02 Sigma    = 2.425 +- 0.1041 Signal/Noise (13cm)Figure 8: Signal to Noise for 13 cm Si strip detector.Since the detectors used in the modules wereoptimised for binary electronics the majority of eventswere single strip hits. Thus the spatial resolution obtainedin the beam test is as expected for binary electronics V =23 Pm (detector pitch 80Pm/12). Selecting events withdouble strip clusters (~15% of total number of events)one can obtain a spatial resolution of about 3Pm. Thedistributions of residuals separately for single and doublehit clusters are shown in figure 9.residual (um.)-50 -40 -30 -20 -10 0 10 20 30 40 500100200300400500600Chi2 / ndf = 51.03 / 11Constant = 615.5 +-  12.7 Mean     = -0.009421 +- 0.04787 Sigma    = 2.892 +- 0.04578 Resolution (double hit clusters)residual (um.)-50 -40 -30 -20 -10 0 10 20 30 40 500100200300400500600Mean  = 0.3891RMS   =   21.7Digital resolution (single hit clusters)Figure 9: Resolution of the 13-cm silicon strip module equippedwith the SCTA128HC chip.An important parameter characterising overallperformance of the detector module is the noiseoccupancy for a given tracking efficiency. The plotshowing the noise occupancy versus tracking efficiencyfor tested modules is presented in figure 10. For theefficiency calculation only events with one well-reconstructed track were considered.Efficiency (%)98.5 98.6 98.7 98.8 98.9 99 99.1 99.2 99.3Noise occupancy (%)10-510-410-3Efficiency vs. NoiseFigure 10: Noise occupancy versus efficiency for 13-cm siliconstrip detector module equipped with SCTA128HC chips.IV. SCTA128VG - A NEW VERSION OF THEANALOGUE CHIP.Although the SCTA128HC chip has been usedsuccessfully over the last two years to build detectormodules one should not forget that this prototype hassome limitations and should not be considered as a finalversion of the analogue chip. Development of the binarychip ABCD in the same DMILL technology has had a bigimpact on the planned improvements in the new versionof the analogue chip. Apart from the changes implied bymodified technology such as the introduction of new rad-hard resistors (RBXB type) and new structures for theinput pads with a screening layer preventing parasiticcoupling through the substrate, several improvements infront-end part have been done. In April 2000 a newversion of the analogue chip SCTA128VG was submittedto the TEMIC foundry. The first stage of the preamplifieris identical to the ABCD3T design (the noise performanceand radiation hardness is already proved).In the new design of the shaper stage we focused onthe improvements of PSRR, immunity to spread of theprocess parameters, temperature and drifts duringirradiation. The overall gain of the front-end stage wastuned to 50 mV/fC to be completely safe against the ADBpedestal spread and possible excess noise at the level ofdata transmission outside the chip. The stability of thefront-end parameters with respect to temperature isimproved by using a new band-gap reference for the biasDAC’s. Several changes in structure of the biasing andgrounding of the front-end stage both on schematic and atthe layout level have been applied to improve the stabilityof the chip working in detector system with millions ofchannels.The schematic of one channel of the front-endamplifier is shown in figure 11. The input stage formedby the bipolar transistor loaded with a PMOS currentsource is followed by a common collector buffer andenclosed with the transresistance loop.  A DC coupledbooster amplifier provides extra amplification before theshaper stage. A booster amplifier is a two-stage BiCMOSamplifier with negative feedback defined by a resistivenetwork. It provides good stabilisation of the gain withrespect to the technological parameters, temperature andpower supply as well as high bandwidth for relativelysmall power consumption (0.25 mW for nominal bias).The same structure is replicated in the shaper stage, whichis AC coupled to the preamplifier in order to preventpropagation of DC offsets implied by the spread ofprocess parameters and drifts after radiation. An extra ACcoupling is used in the front of the output buffer in orderto provide a well-defined DC level at the output of thechip before the optical link. One can notice the separationbetween grounds and supplies lines, especially the extraconnection for the emitter of the input transistor – themost sensitive node of the circuit – to avoid parasiticcoupling via the common inductances of the bond wires.The bias lines used in various part of the amplifier areseparated and filtered to avoid parasitic coupling of thehigh dynamic range signals to the more sensitive frontpart of the circuit.During the optimisation of the circuit we have placedspecial emphasis on the reduction of possible variationsin the circuit parameters with operating conditions(temperature and power supply) and the variations ofprocess parameters from run to run. In order to illustratepossible effects we show in figure 12 and 13 simulationresults for gain and peaking time respectively for variouscombinations of power supply (r10%), operatingtemperatures (0 and 80oC) and corner parameters definedby the technology vendor.Vref=1.6V;RSET(-1,2);PSET(0,8);Input = 12fC0 5 10 15 20 25 30 35Gain (V/fC)0.040.0450.050.0550.060.0650.07V 3.6 T 0V 3.6 T 80V 4 T 0V 4 T 80V 4.4 T 0V 4.4 T 80ttFRnom-25% Rnominal Rnom+25% Rnom+50%Figure 12: Evolution of gain [V/fC] with variation of theprocess parameters (resistors –25% - +50%, CMOS cornerparameters, temperature from 0 to 80oC, power supply r10%).The variation of the parameters are from batch to batch. For agiven batch the matching of the device parameters on chip/waferis much better.Vref=1.6V;RSET(-1,2);PSET(0,8);Input = 12fC0 5 10 15 20 25 30 35Peaking Time (ns) 152025303540V 3.6 T 0V 3.6 T 80V 4 T 0V 4 T 80V 4.4 T 0V 4.4 T 80ttFRnom-25% Rnominal Rnom+25% Rnom+50%Figure 13: Evolution of the peaking time [ns] with variation ofthe process parameters (resistors –25% - +50%, CMOS cornerparameters, temperature from 0 to 80oC, power supply r10%)The corner parameters include also worst casecombinations of initial parameters and expected radiationeffects after a total dose of 10 Mrad. The performance ofthe circuit for 50% higher values of the resistances is onlyshown as an example of the robustness of the circuit sincethe maximum expected deviation is 25%.V. CONCLUSIONSThe SCTA chip is an implementation of full analoguereadout architecture compatible with the requirements forreadout of silicon strip detectors at LHC experiments.Using prototype SCTA128HC chips a number of silicondetector modules matching ATLAS specification hasbeen built and successfully tested in the SPS beam. Anew version of the analogue chip – the SCTA128VG isexpected soon back from the foundry.VI.  REFERENCES[1]  W. Dabrowski et al., Design and Performance of theABCD Chip for the Binary Readout of Silicon StripDetectors in the ATLAS Semiconductor Tracker.Proc. of the IEEE Nucl. Science Symposium, Seattle,IEEE Trans. on Nucl. Sci., in print.[2]  D. Campbell et al., The ATLAS binary chip. SecondWorkshop on Electronics for LHC Experiments,Balatonfured September 23-27, 1996,CERN/LHCC/96-39.[3] J. Kaplon et al., DMILL Implementation of theAnalogue Readout Architecture for PositionSensitive Detectors at LHC Experiments. FourthWorkshop on Electronics for LHC Experiments,Rome, September 21-25, 1998, CERN/LHCC/98-36.[4]  W. Dabrowski et al., Performance of a 128 ChannelAnalogue Front-End Chip for Read-Out of Si StripDetector Modules for LHC Experiments. Proc. of theIEEE Nucl. Science Symposium, Seattle, IEEETrans. on Nucl. Sci., in print.[5]  F. Anghinolfi et al., Performance of the ElectricalModule Prototypes for the ATLAS Silicon Tracker.Fifth Workshop on Electronics for LHCExperiments, Snowmass September 20-24, 1999,CERN/LHCC/99-33.Figure 11: Schematic of one channel of the SCTA128VG front-end amplifier.

Analogue read-out chip for Si strip detector modules for LHC experiments

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