Baumeister, D

Feuerstack-Raible, M

Harnew, N

Hofmann, W

Knöpfle, K T

Löchner, S

Schmelling, M

Sexauer, E

Smale, N J

Van Bakel, N

Van den Brand, J F J

Verkooijen, H

CERN Document Server

Design of a comparator in a 0.25µm CMOS technology.Niels van Bakel, Jo van den BrandFree University of Amsterdam / NIKHEF AmsterdamHans VerkooijenNIKHEF AmsterdamDaniel Baumeister, Werner Hofmann, Karl-Tasso Knoepfle, Sven Loechner,Michael Schmelling, Edgar SexauerMax-Planck-Institute for Nuclear Physics, HeidelbergMartin Feuerstack-RaibleUniversity of HeidelbergNeville Harnew, Nigel SmaleUniversity of OxfordNIKHEF, Kruislaan 409, 1098SJ Amsterdam,Netherlandshansvk@nikhef.nlAbstractA comparator for the LHCb readout chip, the Beetle,has been designed in a 0.25µm CMOS technology and issent for fabrication. To improve threshold uniformity,each comparator has a 3 bits DAC. The comparator canhandle positive and negative input signals. A polaritysignal changes the polarity of the threshold level andmakes the output signal always active high. The outputsignal is latched by a 40MHz clock and is selectablebetween time-over-threshold mode (in 25ns bins) and onepulse mode (25ns). Simulation results will be discussed insection II.I. INTRODUCTIONFor fast primary vertex reconstruction and pile-uprejection, binary hit information is needed from the LHCbvertex detector front-end electronics. Therefore acomparator for the Beetle chip has been designed.Figure 1: Block diagram of the Beetle chipThe Beetle is a 128 channel analog pipeline chip forthe LHCb experiment and can either be used as an analogpipeline chip or as binary pipeline chip. Each channelconsists of a charge sensitive preamplifier / shaper, ananalog pipeline of a programmable maximum length of160 stages with integrated derandomizing buffer of 16stages and a serial read-out for up to 40MHz read-outspeed. In case of using the chip as binary pipeline thediscriminated output of the shaper is stored into thepipeline and a fast binary multiplexer is used to read outthe chip at a speed of 80MHz maximum.The comparator is, like the Beetle, implemented in a0.25µm CMOS technology, using rad-tolerant layoutrules.To make the comparator insensitive for low frequencyinput signals, e.g. temperature drift and different offsets,one of the inputs of the comparator has a low-pass filterto obtain the DC-level of the incoming signal. This levelis summed to the threshold level. The threshold levelconsists of a controllable level used for all comparators(global) and an individual level controlled by a 3 bitsDAC for each comparator (local).The comparator output signal is latched at a well-defined time by a 40MHz clock, which is related to thebunch crossing frequency. The width of the analogcomparator input signals is on average 40ns and thereforethe time-over-threshold can be longer than one period. Bymeans of an "output mode selection" the output signal canbe in time-over-threshold mode (in 25ns bins) or in onepulse mode (25ns) once the input signal went overthreshold.The comparator can deal with positive and negativeinput signals. A polarity signal switches the polarity ofthe threshold level and controls the output stage in such away that the comparator output signal remains positive.In addition a multiplexer has been designed to storehits as binary information. The multiplexer selectsbetween the front-end shaper output and the comparatoroutput and converts the digital comparator signal in a 0 or10 MIP analog signal before sending it to the analogpipeline.Figure 2: Block diagram of the comparatorIn the following subsections each block in the designwill be explained in more detail.A. Low-pass FilterThe comparator-input signal from a front-endamplifier-shaper combination consists of a DC-level witha shaped pulse. The DC- level depends on temperature,offsets and bias settings in earlier stages. To make thethreshold level insensitive for these fluctuations, the DC-level is obtained with a low-pass filter and added to thethreshold level.Figure 3: Low-pass filterThe low-pass filter consists of a capacitor and aresistor. The capacitor is made by the gate-sourcecapacitance of a transistor and is about 2.3 pF. Theresistor is made by a long channel transistor and has aresistance of about 2 MΩ. So the time constant is about5µs.A disadvantage is that also the signal pulses areintegrated which causes an error voltage in the thresholdlevel. The size of this error voltage depends on the signalpulse amplitude and the repetition rate.Error voltage = pVtTt⋅−  [V]Where t is the width of the signal pulse [40ns shapingtime], T is the repetition rate [s] and Vp is the amplitudeof the signal pulse [V].Assume a channel receives a hit every µs (1MHz).The error of the threshold voltage will be about 4% of thesignal pulse amplitude and will not have a bigconsequence for the performance of the comparator.Error voltage = ⋅− 40100040 100mV = 4.2mVThis is simulated in simulation 4 (figure 15)B. AdderThe adder consists of a source-follower and a resistor.The source-follower buffers the output voltage from thelow-pass filter. The threshold level is the voltage on thesource plus or minus the voltage drop across the resistor.This voltage drop is made by a current (I threshold) fromthe threshold circuit (figure 5).Figure 4: AdderC. ThresholdThe controllable threshold level is the sum of a levelused for all comparators (global) and an individual levelcontrolled by a 3 bits DAC for each comparator (local).The sum is converted into a current (I threshold) and isused for the adder above (figure 4). The threshold currentcan be switched positive or negative, depending on thepolarity of the input signal.Figure 5: Threshold circuitD. ComparatorThe comparator consists of two differential amplifierswith a gain of 30 x. The first stage has a differentialoutput to use its gain twice. A buffer decreases the gainwith 0.7 x. So the total gain is 0.7 x 2 x 30 x 30 = 1260.This is simulated and can be seen in figure 14.The signal input has a source follower to keep the DC-levels on both inputs the same. The source follower of thethreshold input is placed in the adder (figure 4).With a polarity signal the output signal can beinverted. This makes the output signal always active high,in spite of the polarity of the input signal.Figure 6: ComparatorThe circuits of the two inputs are symmetrical to makean accurate comparison of the input signals. This can beseen in the circuit diagram of the comparator (figure 8).The transistors with the same function are paired andmatched. Matching tolerances are minimized byappropriate layout techniques. An example is given forthe two buffers.Figure 7: Layout example for better matchingFigure 8: Circuit diagram of the comparatorE. Output sampling & Mode selectionThe output signal of the comparator is latched at awell-defined time. This latch is clocked by a 40MHzclock, which is related to the bunch crossing frequency.The time-over-threshold can be longer than oneperiod. By means of an "output mode selection" theoutput signal can be in time-over-threshold mode (in 25nsbins) or in one pulse mode (25ns) once the input signalwent over threshold.Figure 9: Output sampling & Mode selectionThe 2 modes of output selection are simulated and canbe seen in figure 10Figure 10: Two modes of operationF. Signal converter & MultiplexerFor fast primary vertex reconstruction and pile-uprejection, binary hit information is needed from the LHCbvertex detector front-end electronics. Therefore one canselect between binary information from the comparatorand an analog signal from the shaper. The selection isdone with an analog multiplexer and the digital outputvoltage of the comparator has to be converted into 0 or 10MIP analog signal.Figure 11: Signal converter & MultiplexerII. SIMULATION RESULTSA. Simulation 1The input signal (F/E shaper output) is swept from 1to 10 MIP. The shaper output is about 16mV per MIP.The threshold level is set just below 5 MIP. In the figure12 one can see successively the input signal, thecomparator output signal, the sampled output signal of thecomparator and the sampling clock. As expected theoutput signal is only active when the input signal is 5 MIPor more.Figure 12: Output signals Vs input signal at a 5 MIP thresholdlevelB. Simulation 2The threshold level is set to 0.5 MIP. Now all inputswill generate an output signal. In figure 13 one can seethe time-walk from 1 to 10 MIP. This is about 8ns.Figure 13: Output signals Vs input signal at a 0.5 MIP thresholdlevelC. Simulation 3As calculated in subsection “D. Comparator” the gainis about 1260 times. With a power supply voltage of 2.5Vthe input signal must go 2mV above threshold to make afull swing output signal. In the figure 14 the input signalswings +/- 2mV around the threshold level and the outputsignal goes from ground to Vdd.Figure 14: Output signal Vs 2 mV input signalD. Simulation 4In this simulation the behavior of the low-pass filter(figure 3) is simulated. Every micro second the filter getsan input signal with a pulse width of 40ns and anamplitude of 100mV. The output signal climbs with atiming constant of 5 µs to 4.8mV, which is almost the4.2mV as was calculated in subsection “A. Low-passfilter”.Figure 15: Output signal filter Vs an input signal every microsecondThe simulation results are summarized in Table 1.Table1:  Comparator specificationsInput range GND+0.8V < Uin < VDD–0.8VTime-walk 8nsMin. detectable pulse 2mV above thresholdPower consumption 350µWIII. LAYOUT DESIGNThe layout of the comparator (without the outputsampling and analog multiplexer), low-pass filter andthreshold circuit is shown in figure 16 and 17. The size ofthe design is 107 x 40 µm.Figure 16: Placement of the components on the layoutFigure 17: Layout of comparator, threshold circuit and low-passfilterIV. WORK TO BE DONEThe comparator will be tested in a Frontend-Comparator test-chip and in the Beetle 1.0 chip.Output DC-signal variations of frontends andcomparators will be measured to obtain more informationabout the matching tolerances. With the threshold DACone can compensate for some mismatch, but if one cancompensate for the DC-signal variations of allcomponents, the low-pass filter can be omitted. Theresults will be implemented in the next submission of theBeetle chip, which is planned in spring 2001.V. CONCLUSIONThe simulation results show that the comparatorworks as was intended and that it meets the requirements[2] as foreseen for the pile-up detector.VI. REFERENCES1. Wolfgang Fallot-Burghardt, “A CMOS Mixed-SignalReadout Chip for the Microstrip Detectors of HERA-B”, A thesis for his examination for the doctorsdegree., 24 June 1998.2. M. Feuerstack-Raible, “Beetle – A Readout Chip forLHCb”, http://wwwasic.ihep.uni-heidelberg.de/lhcb/3. Willy M.C. Sansen, Zhong Yuan Chang, “Low-NoiseWide-Band Amplifiers in Bipolar and CMOSTechnologies”, Kluwer Academic Publishers, 1991,ISBN: 0-7923-9096-2.4. AMS, Analog & Mixed Signal Application Note –Device Matching rules.

Design of a comparator in a 0.25 $\mu m$ CMOS technology

Design of a comparator in a 0.25 $\mu m$ CMOS technology

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Design of a comparator in a 0.25 μm\mu mμm CMOS technology

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Design of a comparator in a 0.25 $\mu m$ CMOS technology