Baur, R

Erdmann, W

Gabathuler, K

Horisberger, R P

Kotlinski, Danek

Schnyder, R

CERN Document Server

Readout of the CMS Pixel Detector.D.Kotlinski, R.Baur, K.Gabathuler, R.Horisberger, R.Schnyder, W.ErdmannPaul Scherrer Institut, 5232 Villigen, Switzerlanddanek.kotlinski@psi.chAbstractThe design of the readout of the CMS pixel detector ispresented. The basic detector layout is shown together withthe data rates expected at full LHC luminosity.  The pixelreadout chip is described and the scheme for the transfer ofthe trigger confirmed data is outlined. The integration of thepixel readout system into the CMS DAQ system is shown.I. DETECTOR LAYOUTThe task of the CMS pixel detector is to provide highresolution 3D space points required for the track patternrecognition and for b-tagging.Two barrel layers of the pixel detector will be located atmean radii 4.3 cm and 7.2 cm with a third layer at 11.0 cmadded later. The pixel barrel will be 53 cm long and will besupplemented by two end disks on each side (see Figure 1). Inorder to achieve the optimal vertex position resolution in boththe (rΦ) and the z co-ordinates a design with a square pixelshape 150×150 µm2 was adopted.Figure 1: Perspective view of the CMS pixel system.To enhance the spatial resolution by analogue signalinterpolation the effect of charge sharing induced by the largeLorentz drift in the 4 T magnetic field is used. Hence thedetectors are deliberately not tilted in the barrel layers but aretilted in the end disks resulting in a turbine like geometry. Theuse of signal interpolation means that full analogueinformation has to be transferred from each hit pixel.The whole pixel system consists of about 1500 detectormodules arranged into half-ladders of 4 identical moduleseach in the barrel and blades with 7 different modules each inthe disks.To read out the detector about 16000 readout chips arebump-bonded to the detector modules. The total number ofreadout channels (pixels) is about 45*106. More detaileddiscussion of the detector layout and geometry can be foundin Ref. [1].A picture of the CMS barrel pixel module is shown inFigure 2. A 65.9 mm long, 17.45 mm wide and 250 µm thickSi sensor has 16 readout chips (ROCs) bump-bonded to it.Each ROC reads 53 (rows) * 52 (columns) pixels and includesa column periphery and an interface area.Figure 2: View of a barrel module. In the insert the vertical scale israised by a factor of 5.The ROCs are glued to a 270 um thick Si base plate whichcan be attached to the cooling frame. A 50 µm Kapton hybridis glued on the top of the sensor. The readout chips are wirebonded to the hybrid circuit. On the hybrid, clock and controlsignals arriving via a copper-on-Kapton cable are distributedto the readout chips, involving the Token-bit manager chip(TBM), and the hit signals from triggered events are sent by adriver chip through the same Kapton cable to the barrelperiphery mounted at the ends of the barrel. Power is broughtfrom the barrel periphery to the hybrid via aluminium wires.The Kapton cable is glued and wire bonded to the hybrid.The bump-bonding procedure using Indium has beendeveloped at PSI. The end-cap detector modules aresomewhat different. Due to the blade design the sensor areavaries in size from 2 ROCs to 10 ROCs.II. DETECTOR  READOUTA. Data ratesAt full LHC luminosity about 1000 tracks cross the pixelbarrel layers every 25 ns. Out of these less than 50 tracks areinteresting from the physics point of view (pT > 1 GeV). Therest have either low momenta or belong to pile-up events.For the barrel layer at 7 cm about 3300 pixels are hit every25 ns. On the average 15 pixels are hit in one barrel modulewhich translates into an occupancy of 3.3 * 10-4 or a singlepixel counting rate of 10 kHz. Since the readout is double-column oriented it is of interest to note that a double-columnis hit at a 0.6 MHz rate (occupancy of 1.5%) and on theaverage a hit column will register 2 hit pixels.The overall number of hit pixels per event is 1.3 * 104,which, assuming 3 Bytes of information per pixel, translatesinto a data volume of about 40 kBytes/event. At the nominal100 kHz trigger rate this results in a 4 GBytes/s data flow.Figure 3: Conceptual layout of the pixel readout chip.B. Readout SchemeReadout chips are organised in double-columns. Eachdouble-column consists of a group of 106 pixels and aperiphery circuit.  Figure 3 shows the overall layout of thereadout chip, while Figure 4 presents the column peripherycircuit in more detail.Each pixel cell consists of analogue and digital parts. Theanalogue part has an amplifier, shaper and a comparator. Thethresholds of the comparator are individual programmed foreach pixel using a 3-bit DAC. Only signals that are above thethreshold are allowed to trigger the digital part of the circuit.Pixel cells within one double column are connected to itsperiphery with a set of local bus lines, one of them being theColumn-OR which combines all pixel cells in a doublecolumn into a global OR. Hit pixels use this Column-OR tonotify the periphery about a new event. The data are then readout in two stages.The first stage, called the column drain cycle, takes placewithin each double-column and runs at 40 MHz. The timeinformation is stored (within 25 ns) in the time-stamp bufferand the address and the analogue signal of each hit pixel istransferred as fast as possible to the column data bufferlocated in the column periphery. For the average of 2 pixelshit per double column, about 6 clock cycles (at 40 MHz) arerequired to complete the readout.Figure 4: Schematics of the column periphery mechanism withmultiple time-stamp and data buffer management.This data has to be stored for 3.2 µs while waiting for the1st level trigger (1LT) decision. For every clock the bunchcrossing counter (BC in Figure 4) stored in the time stampbuffer is compared with the search counter (Search BC).  Ifboth agree the time stamp is considered for triggerconfirmation (T1 signal in Figure 4).10.45  mm8.00  mm  Time-stamp     &     Readout  BusControl  &  Interface  BlockI   C - DAC's2Power supply  &   Clock  PadsReadout  Amplifier Tranmsmission        Line  DriverColumn PeripheryABTime StampsData BufferPixel hit Col. ORA=BSearch BCWrite   BCTimestamp w/r ContrT1read out rwData Buffer  write/read ControlDataA0 A8Data valid88833DAC DAC Chip Token  Bit   OutChip Token   Bit   InChip Readout ControlSignal   OutAnalog MultiplexerTrigger  #ColumnReadoutControlclearCol. TokenToken  returnClockThe data confirmed by the 1LT are saved for the secondstage of the readout while the unconfirmed data are erased.The 1LT rate is about 30 kHz, which results in a datareduction factor of 1000.In the second readout stage the triggered data aretransmitted to the CMS data acquisition. The data confirmedby the 1LT are flushed from each double-column and are senton optical links to the readout electronics (Front End Drivermodules - FEDs) 100 m away from the detector. A schematicview of the token bit readout mechanism is shown in Figure 5while Figure 6 shows the overall integration of the pixelreadout in the CMS DAQ system.Groups of 8 or 16 ROCs are connected to one readout link.In order to synchronise the data transmission a token-bitmanager chip (TBM) is used (see Figure 5). This chip,through a token mechanism, controls the access of eachcolumn to the readout link. It also formats data  packets andsignals errors.  The preliminary design of the TBM chip(made by the CMS group from Rutgers University) will beready at the end of 2000 and will initially be implemented in aprogrammable gate array.Figure 5: A schematic diagram of the pixel readout system. The FEDand FEC modules are located in the counting room. The Token-bitmanger chip is placed on the module’s hybrid for the barrel and onthe port cards for the end disks.A data packet is sent through each link for every triggeredevent, even if no pixels were hit. A packet includes a headerand trailer provided by the TBM chip. In addition to theanalogue pixel-charge amplitude  several digital signals haveto be transmitted as well e.g. pixel addresses, columnaddresses, ROC’s IDs and trigger numbers. In order to savebandwidth digital signals are compressed using a 5-6 levelanalogue coding. The exact number of the coding levels willbe determined later when the noise and stability of the opticallinks are known.Both chips, the ROC and the TBM will include I2Cinterfaces in order to be able to program various internalregisters like e.g. pixel thresholds, DAC values or the triggerlatency. The I2C protocol will also be used to read back statusinformation from the front-end system.C. Integration with the CMS Data AcquisitionThe FED modules, located in the counting room, receivedata packets, perform digitisation, format events and sendthem to the CMS DAQ (indicated by the Readout Unit - RUin Figure 6).Figure 6: The integration of the pixel readout in the CMS dataacquisition system.Each FED has 48 input optical links. The circuit in eachinput includes an amplifier and an ADC.  A lookup table isalso needed to decode the packed digital signals. After thesignal processing events are assembled by combining pixelinformation from all 48 inputs. By mixing in one FED linksfrom different pixel layers, we can achieve the 2 kByteaverage event fragment size per FED, required by the CMSDAQ. The FED can buffer up to 100 events. The prototypeROCs+TBM I2C HUBFED FECMonitorWSCrateControlRUDCS TTSTTCviVME 64xClock & T1 & CtrlClock,T1Clock &T1& CtrlDataDataLocal NetworkFrontend9U VMEI2CI2Cpixel FED is being designed by the CMS group from Viennaand will be available in late 2000.The control modules (FECs), also located in the countingroom, send the clock, trigger and all other control and resetsignals down to the detector. The ROC chip programming(e.g. setting of the pixel thresholds) is also done by the FECs.FECs communicate with the front end using the I2C protocol.A faster version of the protocol is developed in order to beable to download the pixel thresholds within a reasonabletime.  In order to limit the number of optical links a I2C-Hubchip is being designed. This chip, placed at the detector, willbe used to distribute the incoming stream from one controllink to a number of detector modules. The I2C-Hub will be astandalone chip or could be included in the TBM chip. Notethat the generic label “CCU” used in Figure 5 has beenreplaced in Figure 6 by a more appropriate “I2C HUB” label.The FED and FEC modules which service the samesegment of the detector will be located in the same VMEcrate. This way both can communicate with the same cratecontroller CPU allowing for efficient system monitoring andfast resets in case of error conditions. Each crate controllercommunicates with a monitoring workstation where moreglobal data diagnostics will be done. Also shown in Figure 6are the standard components of the CMS DAQ system : TTCused to distribute the fast signals,  DCS detector controlsystem and TTS the trigger throttle control.r=7cm, 100kHz, 40MHz, 16-chips, hi/low-lumiFigure 7: Upper figure: The number of hit pixels per data packet forthe pixel layer at 7~cm, the full dots are for the high luminosity andthe open dots are for the low luminosity. Middle figure: The packetreadout time shown in units of LHC clocks.  Lower figure: Thepacket wait time, the peak at 128 clocks corresponds to data packetsbeing transmitted immediately after the arrival of the trigger.Together about 1500 optical links are needed to readoutand control the pixel detector.D. Readout TimeThe number of readout optical links has to be optimised.On one hand this number has to be kept as small as possible inorder to minimise the cost and the material budget. On theother hand the bandwidth has to be sufficient to avoid largedata losses. With the assumption of maximum 100 kHztrigger rate and a 40 MHz analogue link we arrive at thesegmentation presented in Table 1 for the barrel pixels.Table 1: Readout related parameters at high luminosity for a 100kHz L1 trigger rate.Radius [cm] 4 7 11ROCs/link 8 16 16Pixels/link 16±11 15±9 8±6Read. Time [µs] 4 5 4Max. time [µs] 14 13 10Wait time [µs] 1.4 2.4 1.1For example at 7 cm 16 ROCs are connected to a singleoptical  fibre, resulting in an average of 15 pixel hitstransmitted per event. The average readout time is then 5 µs.Due to statistical fluctuations in the number of hit pixels (σ=9at 7 cm), for some events the link will have to readout muchmore data, which might take up to 13 µs.The distribution of the readout time lengths, together withthe histogram of the number of pixels per link, are shown inFigure 7. While the average number of pixels per link is 15the tail of the distribution extends up to 50 pixels, resulting invery long data packets. The readout system should be able todeal with such cases and not time-out too early.Figure 8: The TBM stack counter occupancy. The solid line is for a100 kHz 1LT rate and the dashed line is for 30 kHz. The upper figureis for the pixel layer at 7 cm and the lower one is for 4 cm.Sometimes the readout will still be busy with the previousevent and triggers will have to be queued in the TBM chip.The average waiting time after the arrival of the trigger is alsoshown in Figure 7. Most of the time the data packet is sentimmediately after the arrival of the trigger (note the sharppeak at 128 clocks in the lower part of Figure 7), for someevents however the waiting time can be as long as 1000clocks (25 µs).To queue triggers the TBM chip requires a buffer of asufficient size. Figure 8 shows the average occupancy of thesebuffers for pixel layers at 4 and 7 cm at high and lowluminosities and for typical trigger rates. From these plots onecan conclude that a size between 8-16 is sufficient. The TBMchip is designed to react when the number of queued triggersis above a certain programmable value. It then blocks triggersfrom reaching the ROCs and sends empty data packets to theFED with an error code asking for a rest.III. READOUT CHIP DEVELOPMENTA simplified 22*30 readout chip has been designed andproduced in 1998 both in the DMILL (DM_PSI30) andHoneywell RICMIS IV (HW_AC30) technologies. In thosechips the time-stamping mechanism was present but the zero-suppression within a double column and the data buffers werenot implementedSince then all required functional components have beendesigned and tested on independent test structures.  In July2000 a fully featured chip has been submitted to DMILL(DM_PSI41). It is a 36*40 pixel array and includes all blocksneeded for the LHC operation at full luminosity :1. A fully functional pixel cell (with 127 transistors/cell).2. A fast (1.8 GHz) empty pixel skipping mechanism.3. A 9 * 8 bit time stamp buffer in each double column.4. A 24*4 analogue data buffer in each double column.5. 2 * 8 bit clock counters and 2 * 4 bit trigger counters.6. A pixel programming mechanism, which includes a 3 bitthreshold and a 1 bit disable switch.7. A safety mechanism to bypass defective pixel cells anddefective columns.The chip is expected to arrive for testing in January 2001.The final readout chip is planned to be submitted in spring2001.In our, column drain architecture design, the hit pixels arecontinuously readout by the fast scan mechanism running at1.8 GHz. One of the main concerns has been a possible crosstalk between the digital search signals and the analogue circuitin a pixel unit cell. In a recent measurement [2] thiscontribution has been determined to be less than 500electrons, which is small comparing to the planned thresholdof 2500 electrons.IV. REFERENCES[1] CMS The Tracker Project Technical Design Report,CERN/LHCC 98-6, 15 April 1998.[2] Roger Schnyder, Diplomarbeit Fachhochschule Zuerich,September 2000.

Readout of the CMS pixel detector

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