Bota, S

Diéguez, A

Garrido, L

Gascón, D

Roselló, M

CERN Document Server

A BiCMOS discriminator interface for the SPD.Diéguez, A., Bota, S.Departament d’Electrònica, Sistemes d’Instrumentació i Comunicacions, Universitat de Barcelona, C/Martí Franquès,1, E-08028, Barcelona, Spain.dieguez@el.ub.esGascón, D., Garrido, L.Departament d’Estructura i Constituents de la Matèria, Universitat de Barcelona, C/Martí Franquès, 1, E-08028,Barcelona, Spain.Roselló, M.Departament d’Electrònica, Enginyeria i Arquitectura La Salle, Universitat Ramon Lull, Pg. Bonanova 8, E-08022,Barcelona, Spain.AbstractA prototype chip for the analogue readout of the SPDin the LHCb Calorimeter is presented. The chip has beendesigned using the 0.8mm-BiCMOS technology of AMSand optimised for minimum size and maximumperformance at the required frequency of operation inLHC experiments. It consists of a dual structure formedby two integrators, two track and hold circuits, twosubstractors, two comparators and a multiplexer. The diesize occupied by one discriminator circuit isapproximately 1720 mm x 330 mm.I. INTRODUCTIONLHCb is dedicated experiment to study CP violationand other rare phenomena in B-meson decays at LHC(Large Hadron Collider at CERN). CP violation is one ofthe remaining open questions in experimental particlephysics and cosmology. On the former field, its goal isperform an experimental precision test of the consistencyof the Standard Model. On the later, CP violation is oneof the three necessary conditions to generate matter-antimatter asymmetry, but Standard Model does not seemto be able to generate sufficient CP violation so that theuniverse could be dominated by matter as cosmologyclaims that it is.LHCb [1] is a typical fixed target spectrometer. Itconsists of a vertex detector at the intersection point, atracking system, RICH counters, a large-gap dipolemagnet, a calorimeter system to measure particle energyand a muon system (figure 1). Modern particle detectorshave to cope with very high rates of collisions, for LHCthe bunch crossing clock is 40MHz, and with a very largeamount of subdetectors and sensors. About 949000channels (from 1 to 12 bit of resolution, that means 87KBytes in total) have to be processed each 25 ns. Thisimplies that information rate is of 3.48TBytes/s. It isobvious that is not possible to record or study suchamount of information, for this reason and to select"interesting events" (only at the 0.5% of events there is anuseful decay to study CP violation) a trigger system isdesigned  to discard non interesting event. This system isdivided in 4 levels, each level using only partialinformation. First level, called L0 trigger, has to copewith an input  rate of  40MHz, so it is a pure hardwareprocessing system, the latency of the system is 4 ms andthe output rate is 1MHz. L0 trigger selects particles withlarge transverse momentum, information provided bycalorimeter and muon detectors, and has a pile-up veto.L1 trigger reconstructs partial tracks of particle and hasFigure 1: LHCb detector section view.an output rate of 40KHz. After L2 and L3 trigger,implemented by software, the storage rate is 20Mbytes/s.In the LHCb, the Scintillator Pad Detector (SPD) isplaced just before the Preshower (PS) of theElectromagnetic Calorimeter (ECAL in figure 1). TheSPD is designed to distinguish electrons and photons(ECAL and PS can not do it by themselves) at the L0trigger level. It is a plastic scintillator layer, divided on6000 cells of (4x4 cm at inner part and 12X12 at outerpart cm). Charged particles will produce, and photons willnot, ionisation on the scintillator. This ionizationgenerates at the plastic scintillator blue light that iscollected and converted in green light by Wave LengthShifting (WLS) fibre that is twisted inside the scintillatorcell. This light is transmitted  by a clear fibre to aelectronic system which is placed on the upper on lowerend of the ECAL structure. On the electronic system a 64anode photomultiplier (Hamamatsu R7600-M64 [2])converts the light in charge pulses. The analog circuitdescribed here process the signal to determine if itcorresponds to a photon or to an electron.Several effects complicates the signal processing, themain difficulties are: energy "deposited" by photons andstatistical signal features. Photons are not chargedparticles, therefore one should not expect detect them onSPD, nevertheless they do. Photons deposite energythrough secondary processes like Compton effect or pairproduction. The energy spectra of photons (figure 2)shows that most photons do not deposite energy (largepeak at zero), but there is a small tail overlapped on theelectrons spectra (peak at 2 MeV) which can provokemisidentification. Hence, the analog processing shoulddiscriminate photons (background) and electrons (signal).Taken into account that signal has no real separation frombackground, there is, then, a compromise between triggerefficiency and wrong identification. In order to achievethe maximum efficiencies an individual channelcalibration is needed to compensate tolerances of thedetection system, like the gain fluctuation between thedifferent channels of the photomultiplier which is of theorder of 3. In our system such a calibration can only beperformed by an on-line update and control of thediscriminator threshold for each channel.The second problem is related to the statistical natureof a scintillator detector, and mainly to the desexcitationtime of the WLS fibre. This kind of fibre captures a bluephoton a emits a green one on a time that follows anexponential random distribution with a t of about 10 ns.Finally this produces a random signal shape, we can seean example on figure 3. Studies performed by ourcolleagues of the "Laboratoire of PhysiqueCorpusculaire" at Clermont-Ferrand [3] shows forMinimum Ionising Particle (MIP) a fluctuation of s =50% on the total integral signal and also that only a 83 ±13 % of signal is integrated in 25 ns because the rise timeof the integral signal is 28.88 ± 7.3 ns. Therefore meansignal lasts more than the maximum integration timeallowed: 25 ns (the bunch crossing period). Thisphenomena has two main consequences on the electronicdesign: a dual architecture is needed in order to do nothave any dead time on integration reset and it will be veryprobable to have pile-up. Pile-up means that part of thesignal of the event n is detected on the event n+1, andthere is no way to distinguish from the signal detected onthe event n+1. Although it can not be avoided it ispossible an statistical compensation: a 17% of the integralsignal of the event n is subtracted from the integral signalof event n+1.II. DISCRIMINATOR INTERFACEBecause of the high frequency of the signals in theexperiment (40MHz) and the large number of channels(6000), speed and cost are decisive. This mandates tomake a minimum size design of each channel and usebipolar or BiCMOS technology. BiCMOS technology hasthe advantage that for analog circuits, bipolar devicesoffer a transconductance higher compared to MOSdevices, leading to, for a given area, higher speed andgain. On the other hand, MOS transistors offer simpleanalog switches with zero dc offset voltage, highimpedance charge storage nodes and, complemetarytransistors.The structure of the discriminator presented here isshown in figure 4a. In order to reduce noise the design isFigure 2: Normalised  spectra of deposited energy (inMeV) by high energy photons and electrons obtainedby MonteCarlo simulation.Figure 3: Example of MonteCarlo photomultiplieroutput signal. X axis: time in ns. Y axis: charge inelectrons.completely differential. Because of the jitter of the inputsignal and its non-reproducible shape, the signal comingfrom the photomultiplier has to be integrated rather thanconsidering its maximum value [3]. So, the input deviceof the discriminator is an integrator circuit. On the otherhand, as commented before, to avoid dead integrationtime (the integrator has to be reset between twoconsecutive integrations), a double channel has beenchosen. Each channel of the discriminator is controlled byan opposite clock phase of period 50ns (the double of thebunch crossing frequency). Possible pile-up is correctedthen by subtracting a factor a=17% of the integratedsignal in the clock n from the signal being integrated inthe clock n+1. To do this, the signal integrated in theclock n has to be stored in a track and hold. After thesubtraction has been performed, the signal is comparedwith the value established in the comparator. Finally, afterthe comparators, a multiplexer is added to select thechannel from which the signal is read.So, each channel of the discriminator is controlled byan opposite clock phase and consists on an integrator, atrack and hold, a substractor and a comparator. All theblocks of the circuit are biased between +2.5V and –2.5V.III. BUILDING BLOCKSThe first block of the discriminator circuit is acontinuous time integrator (figure 4b left). It is formed bya large bandwidth and high gain differential amplifier,and the integration capacitors and resistors. The nmosswitches are included to control the integration-resetsequence. It is clear that integration is performed whenthe clock is high. The value of the capacitors and resistorsis 300fF and 5KW.The structure of the differential amplifier used ispresented in figure 4b (right). It consists of a differentialbipolar pair with pmos active load. The crossed pmostransistors give the necessary path for current flow toallow high gain without degrading the large bandwidthobtained with the differential bipolar pair. Anotheradvantage is that no compensation capacitors are neededbecause this amplifier is a single-stage one. Simulateddata show a dc gain Av= 52.7dB, a bandwidthfc=1.38MHz, and a phasemargin PM=82.57º for unitygain frequency fu=589MHz. The total current through theamplifier is 250mA.The design of the track and hold block (T&H) isbased on reference [4]. A fully differential architectureallows to reduce the typical artifacts of T&H circuits, i.e.,pedestal (change in the output voltage during thetransition from track to hold mode), drop rate (decrease ofoutput voltage when in the hold mode), and feedthrough(influence of the input signal on the output in the holdmode). The two first are reduced as a consequence of thefully differential design, while the last needs additionalcompensation. An additional key point of the T&H is theneed of only one clock phase, thus being reducedproblems related to clock generation and routing.The scheme of the T&H presented here is shown infigure 4c. As in reference [4], it consists on an inputbuffer of unity gain, nmos switches, hold capacitors (Chin figure 4c) and output buffers. With respect to reference[4], in the present design, the bipolar switch has beenreplaced by an nmos switch in order to increase thepossible range of the input signal and to simplify thedesign. Moreover, the differential input buffer is onlyformed by a degenerated differential pair (two bipolartransistors and the resistor R2) loaded with resistors R1.The ratio R2=2R1 gives the unity gain condition of theinput buffer needed for a track and hold application.Figure 4: a) Structure of the discriminator circuit. b)Integrator (left) and differential amplifier used in theintegrator circuit (right). c) Transistor-level schematic of thetrack and hold. d) Analog substractor (left) and single-endedamplifier for the substractor (right). e) Comparator circuit.Usually the load of each bipolar transistor of thedifferential pair is a series connection of a diode and aresistor in order to obtain high linearity. For ourapplication the diodes can be omitted. Finally, hold modefeedthrough has been compensated by a feedthroughcapacitor (Cf) connected as shown in figure 4c.The operation of the T&H is as follows. Duringck=high the T&H is in the track mode, i.e., switchesMSW1 and MSW2 are on and Ch is being charged. Whenck=low, the T&H is in the hold mode and there is noconnection between the emitter follower drived by theinput buffer and the hold capacitor. In this mode thecharge in the hold capacitor determines the voltage at thebase of the emitter follower output buffer and, thus, theoutput voltage.The values used in this T&H are Ch=2pF, R1=3KW,R2=2R1=6KW, and Cf=23fF. The current flowingthrough the input buffer and through the two emitterfollowers is 250mA. With these values the simulatedcharacteristics of the T&H for an input signal of 1V are apedestal of 3.1mV, drop rate DR=80mV/ns, and no holdmode feedthrough. A rail-to-rail input range can beobtained by adjusting the resistances and the current inthe input buffer. Between the input signal and the outputthere is always a delay of 1.6ns, corresponding mainly tothe intrinsic delay of the input buffer. The T&H canoperate up to sampling frequencies ~500MHz.The structure of the analog substractor is presented infigure 4d (left). It is needed in this block to convert thedifferential signal coming from the T&H to single endedsignal. Thus, the substractor is composed by four inputresistances, two feedback resistances and, a single-endedamplifier. The structure of the amplifier (figure 4d right)is very similar to that presented in figure 4b (right), but anoutput buffer has been included in one of the outputs. Inorder to compensate the coupling between the inputdifferential stage and the inverting output stage, a seriesRC network (Rc=0.5KW and Cc=500fF) across the secondgain stage provides the frequency compensation. Thesimulated characteristics of the amplifier are a dc gainAv= 61.8dB, a bandwidth fc=493.9KHz, and aphasemargin PM=52.14º for unity gain frequencyfu=539MHz.The operation to be made is S=(Vin2+-Vin2-)-a(Vin1+-Vin1-).  In order to take into account the factor a»17% thevalues of the resistors in the circuit of figure 9 areRf=Rff=R2=R4=5kW, and R1=R3=29.5KW.The schematic of the comparator circuit is shown infigure 4e. An additional input preamplifier can improvethe performance of the comparator but has not beenimplemented because it is not needed for this application.The core of the comparator is the well known latchedcomparator [5]. The latch is clocked by means of a MOSdifferential pair. When clock=high the circuit is in theacquisition phase. In this case the latched comparatorbehaves simply as a differential amplifier (Q1 and Q3loaded with resistances R) for the differential input Vin1-Vin2. When ck=low the comparator is in the regenerationphase. In this case Q1 and Q3 are off and Q2 and Q4 areconducting. Again Q2 and Q4 together with the loadresistances, form a differential pair. It is in this phasewhen the comparator exploits the positive feedback toreach the desired output levels. In the positive feedbackpath there is a buffer formed by the MOS transistors M1and M2 for Q2 and M3 and M4 for Q4. The two outputCMOS inverters appearing in figure 4e are scaled in orderthat the output levels are ±2.5V.The current flowing in the lached comparator and inthe buffers is 120mA. The propagation time of the latchedcomparator is only of ~2ns, which corresponds to amaximum operation frequency of 500MHz. Becausesimulation data are only available it has no meaning totalk about input offset and maximum resolution.The final block of the discriminator is a differential2:1 multiplexer circuit with open drain outputs. There arenot special demands on the characteristics of this circuitas their inputs result from a previous latch.The die size of the functional blocks of thediscriminator circuit are presented in table I. The designwas sent to the AMS foundry on March 2000.Table I: Die size occupied by each block. The discriminator sizeincludes the current sources, the clock generator circuit, andinterconnections between blocks.Block Die sizeIntegrator 185mm x 100mmSubstractor 275mm x 200mmTrack & Hold 205mm x 120mmComparator 150mm x 152mmMultiplexer 90mm x 110mmDiscriminator 1720mm x 330mmIV. RESULTS AND CONCLUSIONThe complete circuit has been simulated usingSpectre as electrical simulator. Figure 8 shows anexample of the operation of the discriminator circuit.Clock signal is the 20 MHz (half the bunch crossingfrequency) channel clock which gates the integrators for25 ns and controls the internal switches. When Clock ishigh the sequence of signal processing works as follows:·  Integrator 1 is integrating the input signal andIntegrator 2 is discharging its feedback capacitors.·  Track & hold 1 follows Integrator 1 signal andTrack & hold 2 holds Integrator 2 signal.·  The output signal of Substractor 1 (sum 1) is theinput signal of Comparator 1, and the value of this signalis: ”Track & hold 1” - 0.17 * ”Track & hold 2”.·  Comparator 1 compares its input signal (sum 1)with Threshold 1, giving at the output (Comparator 1)the transient result of the comparison which will belatched on the next Clock period (when this clock falls tothe low level).·  Comparator 2 is in ”latch” operation holding athis output the result of the previous comparison, which istransmitted to the output of the channel through themultiplexer.A symmetric situation occurs when Clock is low.On this simulation we combine two signals thatcorresponds to the opposite tails of the statisticalfluctuation of the PMT signal. The conditions to definePMT signal are: 1 MIP signal is equivalent to about 35photoelectrons, the high voltage is set to 900 V and theload resistor at the output of the tube is 100. These signalsare approximated by exponential pulses of 50 mV and 10mV with a time constant of about 12 ns. Threshold is setto detect signals of the smallest amplitude. Three differentsituations are simulated:1. At t=25 ns (period 2 2), a pulse of maximumamplitude is integrated. After following all the processingchain a high level on the Comparator 1 output (period 3)indicates that a charged particle has been detected.Therefore, the delay of the processing chain is one cycle.Although the amplitude of the tail of the signal at period 3is high (Integrator 2 signal at period 3) the compensationof 17 % of the signal hold at Track & Hold 1 outputavoids that input Comparator 2 signal (Sum 2signal atperiod 3) exceeds threshold 2. The tail is not taken as new1 MIP signal although its integral value (Integrator 2signal at period 3) is of the same order of the integral(Integrator 2 signal at period 13) of the 10 mV signal thathas been used to adjust Thresholds.2. At t=125 ns (period 6) we have a 50 mVamplitude pulse and on the next bunch crossing (period 7)(half of Clock signal period) a pulse of 10 mV amplitudeis overlapped to the tail of the large one. Both signals aredetected: the big one at the Comparator 1 output at period7 and the small one at the Comparator 2 output at period8.3. At t=300 ns (period 13) a 10 mV small amplitudepulse arrives and it is detected.As a conclusion, the proposed systems seems to full-fill the initial specifications demanded in the LHCbexperiment.ACKNOWLEDGEMENTSWe would like to acknowledge the Spanish CICYT by thefinancial support through the project "Estudio de laviolación de CP con los detectores de partículas HERA-Bi LHCb" coded AEN99-0483.V. REFERENCES[1]  S. Amato et al., "LHCb Technical Proposal", CERN/LHCC98-4, 1999.[2] Y. Yoshizawa, H. Ohtsu, N. Ota, T. Watanabe and J.Takeuchi, "The Development and the Study of R5900-00-M64 for Scintillating / Optical Fibre Read Out" 1997 IEEENuclear Science Symposium Conference Record, vol.1,Alburquerque, NM, USA, 9-15 Nov. 1997. In IEEETransactions on Nuclear Science, 1, 877-881, 1997.[3] G. Bohner, R. Cornat, A. Falvard, J. Lecoq, J. Maulat, P.Perret and C. Trouilleau, "Structure of the signal and Front-end electronic for the LHCb preshower", CERN LHCb 99-018, June 3, 1998.[4] P. Vorenkamp, and J. Verdaasdonk, Fully bipolar, 120-Msample/s 10-b Track-and-Hold circuit, IEEE J. Solid-StateCircuits, 27(7), 988-992 1992.[5] P.J. Lim, and B.A. Wooley, An 8-bit 200MHz BiCMOScomparator, IEEE J. Solid-State Circuits, 25(1), 192-199,1990.Figure 5: Simulation of the complete discriminator.

A BICMOS discriminator interface for the SPD

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