ATLAS Muon TDC test-element group chip (AMTTEG) was developed and tested to confirm the performance of critical circuits of the TDC and measure radiation tolerance of the process. The chip was fabricated in a 0.3 mm CMOS Gate-Array technology. Measurements of critical elements of the chip such as the PLL, and data buffering circuits demonstrated adequate performance. The effect of gamma-ray irradiation, using a Co60 source, and neutron irradiation, using PROSPERO reactor in France, were also examined. The test results revealed radiation tolerance adequate for the operation of the circuits in the environment of the ATLAS MDT

Arai, Y

Emura, T

Fukuda, M

CERN Document Server

PERFORMANCE AND IRRADIATION TESTS OFTHE 0.3 m m CMOS TDC FOR THE ATLAS MDTY. Arai (email: yasuo.arai@kek.jp)KEK, National High Energy Accelerator Research OrganizationInstitute of Particle and Nuclear Studies, 1-1 Oho, Tsukuba, JAPANandM. Fukuda and T. EmuraTokyo University of Agriculture and TechnologyAbstractATLAS Muon TDC test-element group chip (AMT-TEG) was developed and tested to confirm theperformance of critical circuits of the TDC and measureradiation tolerance of the process. The chip was fabricatedin a 0.3 m m CMOS Gate-Array technology.Measurements of critical elements of the chip such asthe PLL, and data buffering circuits demonstratedadequate performance.The effect of gamma-ray irradiation, using a Co60source, and neutron irradiation, using PROSPERO reactorin France, were also examined. The test results revealedradiation tolerance adequate for the operation of thecircuits in the environment of the ATLAS MDT.1. INTRODUCTIONHigh-resolution, low-power and low-cost VLSI TDC’sare required in the ATLAS precision muon tracker (MDT:Monitored Drift Tubes). The MDT requires  about 370 kchannels of sub-nano second TDC to realize  the highresolution of the MDT.Although we have developed several TDCs whichfulfil some of the basic requirements, the ATLAS MDTTDC has more demanding requirements especially in datahandling. Thus we have began a project to develop a newTDC chip called the AMT (ATLAS Muon TDC) [1] incollaboration with the CERN microelectronics group. Tostudy the chip architecture, intensive Verilog simulationswere done [2]. In addition, a quick test chip wasdeveloped in a 0.7 m m CMOS process [3] for a mediumscale test (10 k channels) of muon front-end electronics.Since the mass production of the chip is scheduled foryear 2001, we have selected a relatively advancedprocess, 0.3 um CMOS Gate-Array technology (ToshibaTC220G), for the final TDC chip. This new processprovides a lower per channel cost and higherperformance. In addition, we can expect a longer lifetimefor the process, and, in turn, easier maintenance.To measure the basic performance of the design andconfirm the radiation tolerance of the process, we havedeveloped a test element group chip (AMT-TEG) usingthe 0.3 m m process.The chip contains bare NMOS and PMOS transistors, aring oscillator for radiation tests. Gamma-ray irradiationwas performed with a Co60 source at Tokyo MetropolitanUniversity. Neutron irradiation was performed at thePROSPERO reactor in France.Photograph of the chip is shown in Fig. 1, and a blockdiagram of the AMT-TEG chip is shown in Fig. 2. Thereare 24 input channels in the chip. These inputs areconnected to three 8 ch ASD chips [4] in the MDT design.To reduce number of input pins, only 16 hit input pins areimplemented and selectively connected to internalcircuitry in this AMT-TEG chip.The AMT-TEG chip contains most of circuits used inthe final AMT chip. Only the trigger interface and triggermatching circuit are excluded. In addition some circuitswere simplified and error checking was minimized.Fig. 1. Photograph of the AMT-TEG chip. The size ofthe chip is 5.2 mm by 5.2 mm. Total number of gatesused is about 70 k gates. The large block in the leftside is the 24-ch channel buffer.ClockCoarse CounterHitInputs(16ch)Fine Time (Trailing Edge)Fine Time (Leading Edge)x24..16..16Coarse TimeCoarse TimeChannel(5b)OverflowFlag (1b)Fine Time(5b)Coarse Time(12b)First Level Buffer(128W) : : : :80 MHz:ReadoutFIFO(32W)Parallel to Serial ConverterSerialOut13 x 2ChannelControllerPFCWrite PointerRead PointerStart PointerSerialIn40 MHzChannel Buffer(4W)Pulse Width(8b)Encoder & Formatter:13 x 2JTAG signalsJTAG TAPControllerLVDSDriver/ReceiverRadiationTestCircuitControl & StatusRegistersTrigger Circuit(not included)PLL TestCircuitBuilt InSelf TestPLLAsym. Ring Osc.VgFig. 2. Block diagram of the AMT-TEG chip.Since the detailed operation of the chip is described inother documents [1, 2], only brief explanation is presentedhere.The hit signal is used to store the fine time and coarsetime measurement in individual channel buffers. The finetime measurement is obtained from taps along anasymmetric ring oscillator. The time of both leading andtrailing edge of the hit signal can be stored.Each channel has a 4 word buffer where measurementsare stored until they can be written into the common firstlevel buffer.To achieve a high-resolution time measurement withsufficient stability, Phase Locked Loop (PLL) is used. ThePLL circuit produces a double frequency clock of 80MHz from the LHC clock (40MHz). By dividing the 12.5ns clock period into 16 intervals a time bin size of 0.78 nsis obtained.2. PERFORMANCE TEST2.1  PLL and Ring OscillatorAlthough the chip is designed in a gate-arraytechnology, layout of the time critical parts such as PLLand the asymmetric ring oscillator were designedmanually to achieve high resolution.We determined the jitter of the PLL circuit bymeasuring the oscillation period of each cycle. RMSvalues of the measurements versus frequency and powersupply voltage are plotted in Fig. 3 (a) and (b)respectively. The jitter of the PLL is small (< 140 ps) andstable for the 40-120 MHz frequency range and for supplyvoltages between 2.8 - 3.8 V (normal operating conditionis 80 MHz and 3.3V respectively).The jitter shows a small structure around 90 MHz andthe value is a little worse than that of the previous chip [5]which was fabricated in a 0.5 m m process. However thejitter is still small enough for the MDT detector whichrequires 500 ps resolution. Additional attention will bedirected to the layout around the PLL in next chip toachieve better stability.6005004003002001000stp[ps]12080400PLL Osc Freq [MHz](a) PLL Oscillation Stability vs FreqtpVdd=3.3Vf(PLL):f(IN)=2:125020015010050stp[ps]4.03.83.63.43.23.02.82.6Vdd[V](b) PLL Stability vs Vddf(PLL)=80MHzFig. 3. (a) Stability of the PLL vs. oscillationfrequency. (b) Stability of the PLL vs. supply voltage.300250200150100500f_PLL(MHz)3.02.52.01.51.00.50.0Vg[V]80MHz Sim(best) Sim(typ) Sim(worst) measure.Fig. 4. Simulation and measurement results for theoscillation frequency of the asymmetric ringoscillator versus control voltage Vg.Fig. 4 shows the control voltage (Vg) dependence ofthe asymmetric ring oscillator. Results from simulationsfor worst, typical and best conditions are also indicated.In the present chip, maximum frequency of the oscillatoris 130 MHz, and well beyond that required for the 80MHz operation.2.2  Two Edge SeparationRecording speed of the channel buffer is important tohave a good double pulse resolution or edge separation.Minimum edge separation was determined by reducingpulse width and pulse separation until the hit informationis lost.Fig. 5 shows an example of minimum pulses. Twoleading and two trailing edge timing are successfullyrecorded in the 4 word channel buffer. Since the testinstruments can not generate pulses shorter than 5 ns,actual performance of the chip may be better than 5 ns,which is already far better than the MDT requirement.Fig. 5. Minimum pulses successfully recorded in theAMT-TEG chip.2.3  Data Buffering SpeedThe data transfer speed from the channel buffer to thefirst level buffer is an essential part of this TDCarchitecture. If the channel buffer become full, further hitinformation will be lost. In a Verilog simulation, theprobability of hit loss is very low (< 10-6) for 300 kHzinput rate in all channels.The transfer speed is measured by changing thenumber of simultaneous hit channels and determining theminimum hit interval where all hits are accepted.In Fig. 6 we plot minimum hit interval for N channelsimultaneous inputs. Above the data point all hitinformation is recorded, but if the hit interval is reducedless than the data point, a part of the hit informationbecome lost due to the lack of the transfer capability. Theline in the figure shows expected speed from the circuit.We see the overhead for arbitration is only 2 cycle andsuccessive data transfer occurs at each cycle.6004002000Hit Interval T [ns]24201612840No. of Hit Channels NT = 50ns + 25ns x NchAll hit acceptedPart of hit lostFig. 6. Minimum hit interval for simultaneous hitinputs. System clock cycle is 25 ns. The data pointsshow minimum hit intervals and the straight lineindicates the expected performance from the 2 cyclesplus N cycles required by the design.2.4  Time ResolutionTime resolution was measured by supplying a clocksynchronous hit signal to the input and varying the delaytime of the signal. The result is shown in Fig. 7. The RMSvalue of 305 ps is obtained. This value is worse than thatof previous TDC chip [5] which achieved 250 psresolution, but still has adequate resolution for ourpurpose.4003002001000Counts-2 -1 0 1 2D t[ns]RMS=305 psFig. 7. Time resolution measurement. Input clockfrequency is 40 MHz and time bin is 781.25 ps/bit.The data contains digitization error of 225 ps.2.5  Non-LinearityNon-linearity of the time measurement was measuredby applying a hit signal for which the delay time isuniformly distributed, and counting the number of hitsrecorded in each bin. The Differential Non-Linearity(DNL) and Integral Non-Linearity (INL) are shown inFig. 8 (a) and (b) respectively. Both are small enough(RMS < 70 ps) for our purpose.0.40.20.0-0.2INL[ns]151050TDC countMax=+/-0.13ns, RMS=0.07ns(b)0.40.20.0-0.2DNL[ns]Max=+/-0.14ns, RMS=0.06ns(a)Fig. 8. (a) Differential non-linearity, and (b) Integralnon-linearity measurement.3. IRRADIATION TEST3.1  Gamma-ray IrradiationGamma-ray irradiation test was done at TokyoMetropolitan University with a Co60 source. Theirradiation rate was about 90 rad(Si)/sec, and total doseirradiated was 100 krad(Si). During the irradiation socalled worst bias conditions for MOS transistors ( 3.3 V isapplied to NMOS gate, and no voltage is applied toPMOS gate), were used. To study post-radiation effects,parametric measurements were also done after annealing(1 week at 100 degree C) following the MIL-STD-883method [6].Total dose expected for worst location of the MDTelectronics is 11 krad(Si) for 10 years LHC operation(including a factor 4 safety factor) [7].In a sub-micron process, most severe damage from theionization process is an increase of leakage current. Fig. 9shows drain leak current for NMOS and PMOStransistors. An increase of NMOS drain leak currentabove 25 krad(Si) was seen while no increase is seen inPMOS. Recovery of the pre-radiation condition is seenafter the annealing in NMOS.Threshold voltage shifts of transistors are shown inFig. 10. There is no shift seen in PMOS transistors and aNMOS transistor while small shifts (~100 mV) are seen intwo NMOS transistors. Since these transistors do not haveany protection circuit, the transistors are susceptible todamage. More samples are needed to confirm whether theshift is due to the irradiation or not.Fig. 11 shows variation of oscillating frequency of aring oscillator and supply current. The ring oscillator iscomposed of 33 NAND gates. The oscillating frequencybecomes lower above 50 krad(Si). The total chip currentwas also increased above 50 krad(Si).Considering low dose rate in the LHC environment, wethink the chip can be used safely up to 50 krad(Si), thusthe chip has enough margin to be used in the MDTenvironment.10-1210-1110-10Id[A]Dose[krad]10 100before Irrad. after anneal.(b) PMOS10-1110-1010-910-810-710-610-5Id[A](a) NMOSFig. 9. Drain leakage current of (a)NMOS and(b)PMOS transistors. Left-most and right-most pointsshow the value before irradiation and after 1 week at100° C annealing respectively.0.80.60.4Vth[V](a) NMOS-1.0-0.8-0.6Vth[V]Dose[krad]10 100before Irrad. after anneal.(b) PMOSFig. 10. Threshold voltage shifts of (a)NMOS and(b)PMOS transistors.Table 1. Summary of the measurements and therequirements.Measurements RequirementsPLL frequency 40 - 120 MHz 80 MHzPLL operating voltage 2.8 - 3.8 V 3.3 VCoarse time counter speed 120 MHz > 80 MHzLVDS interface > 100 MHz > 40MHzMultiple edge resolution < 5 ns < 30 nsL1B transfer speed (2+N) cycle  (4+N) cycleTime resolution 305 ps RMS < 500 ps RMSDiff./Int. Non-Linearity < 70 ps < 300 ps150100Osc. Freq.[MHz] Chip 1 Chip 21.00.50.0Idd[A]1 10 100Dose[krad]before irradiation Chip 1+2Fig. 11. (a) Oscillation frequency of a ring oscillator,(b) Total current of two chips. Left-most points showthe value before irradiation.3.2  Neutron IrradiationNeutron irradiation was done at the PROSPEROreactor facility in France. Eight chips were exposed toneutron flux of 1.0 x 1013 and 4 chips were exposed to 1.6x 1013 n/cm2 (1 MeV neutron equivalent). During theneutron exposure, chips are placed in a conductive plasticcase. The expected neutron flux at MDT front-endelectronics for 10 years of LHC operation is less than 1.2x 1013 n/cm2 (including safety factor 4) [7].After cooling of the radioactivity (~ 2 months), wemeasured transistor parameters and ring oscillatorfrequency. We have not observed any apparent change inall sample chips.4. SUMMARYA test-element group chip (AMT-TEG) for the ATLASMuon TDC was developed for circuit performance test.Radiation tolerance was also measured for gamma-rayirradiation and neutron exposure.Table 1 summarize the results of the presentmeasurements and requirements of the TDC. The AMT-TEG chip demonstrated adequate circuit performance forthe MDT TDC. In addition, the 0.3 m m process showedadequate radiation tolerance for both gamma ray andneutrons at the radiation level of MDT front-endelectronics.AcknowledgementsWe are grateful to J. Christiansen and CERNmicroelectronics group for their help on the chiparchitecture study. Authors would also like to thank, R.Richter for help on the neutron exposure, and R. Hamatsufor help on the gamma-ray irradiation.5. REFERENCES[1] Y. Arai and J. Christiansen, "Requirements andSpecification of the TDC for the ATLAS Precision MuonTracker", ATLAS Internal Note, MUON-NO-179, May1997.[2] Y.Arai and J. Christiansen, "TDC Architecture Study for theATLAS Muon Tracker", Proceedings of the Third Workshopon Electronics for LHC Experiments, London, Sep. 1997.CERN/LHC/97-60, pp315-319.[3] J. Christiansen, "AMT-0 User Manual",http://pcvlsi5.cern.ch/MicDig/amt.htm.[4] E. Hazen, J. Shank, J. Huth, J. Oliver, and W. Riegler, " AnIntegrated Multi-Channel Readout for ATLAS MonitoredDrift Tubes", Proceedings of the Second Workshop onElectronics for LHC Experiments, Balantonfured, 1996.[5] Y. Arai and M. Ikeno; “A Time Digitizer CMOS Gate-Arraywith a 250 ps Time Resolution”, IEEE Journal of Solid-StateCircuits, Vol. 31, No. 2, Feb. 1996, p.212-220.[6] Test Method and Procedures for Microelectronics, MIL-STD-883, Method 1019.4.[7] Atlas policy on radiation tolerant electronics (Draft 2).http://www.cern.ch/Atlas/GROUPS/FRONTEND/radhard.htm

Performance and Irradiation Tests of the 0.3 $\mu$ m CMOS TDC for the ATLAS MDT

Abstract

Similar works

Full text

Available Versions

CERN Document Server

Performance and Irradiation Tests of the 0.3μ\muμm CMOS TDC for the ATLAS MDT

Abstract

Similar works

Full text

Available Versions

CERN Document Server

Performance and Irradiation Tests of the 0.3 $\mu$ m CMOS TDC for the ATLAS MDT