Berst, J D

Colledani, C

Croix, J

Della Negra, R

Deptuch, G

Dulinski, W

Dupanloup, M

Gardien, S

Goerlach, U

Hoffmann, C

Hu, Y

Hu-Guo, C

Le, T D

Schmitt, P

Sohler, J L

Turchetta, R

Zinzinus, Y

Berst, J.D.

Colledani, C.

Della Negra, R.

Deptuch, G.

Dulinski, W.

Dupanloup, M.

Gardien, S.

Goerlach, U.

Hoffmann, C.

Hu Guo, C.

Hu, Y.

Le, T.D.

Schmitt, P.

Sohler, J.L.

Turchetta, R.Zinginess Y.

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The APVD readout circuit for DC-coupled Silicon detectors

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  The APVD Readout Circuit for DC-Coupled Silicon Detectors J.D.Berst1, C.Colledani1, J.Croix2, R.Dellanegra3, G.Deptuch2, W.Dulinski1, M.Dupanloup3, S.Gardien3, U.Goerlach2*, C.Hoffmann2, C.Hu-Guo2, Y.Hu1, T.D.Le2, Ph.Schmitt2, JL.Sohler1, R.Turchetta1, Y.Zinzinus1 [1] LEPSI and [2] IReS Strasbourg,  [3]IPNL Lyon  FRANCE *Ulrich Goerlach, IReS, Strasbourg, France  goe@sbghp3.in2p3.frAbstract The APVD[1,2], an integrated circuit for the front-end electronics of DC-coupled silicon detectors has been developed and produced in the radiation-hard process DMILL for the CMS experiment. This paper reports very briefly on the final test results, more details will be published elsewhere.  I. SUMMARY The APVD_DC contains, like other members of the APV[3] family 128 identical analogue channels, each com-posed of a low noise preamplifier, a CR-RC shaper, an analogue pipeline of 160 cells and a signal processing stage[1,2]. A current compensation circuit is added in every preamplifier to sink the leakage current coming from a DC coupled silicon detector. The circuit has been tested and measured in the presence of significant DC-currents up to 11 microampere, without deterioration of the analogue performance of the circuit like pulse shape or dynamic range. The noise increases by about 300 ENC as is shown in figure 1, small compared to the additional shot-noise.  Figure 1: The measured noise in the presence of different external currents. Previous APVD circuits suffered from an instability problem in the analogue stage of the circuit occurring at nominal bias values. The analogue baseline of the new modified circuit is absolutely stable also under extreme operation conditions, like twice as high bias currents, demonstrating that the implemented solution stops indeed the oscillation of the circuit as we previously claimed based on extensive simulations of the circuit[4].  The linearity and pulse shape are well within the specifications as previous versions of the circuit. More details on the performance will be available in[5]. Figure 2: Pulse shape at nominal and increased bias conditions.  II. REFERENCES 1 R. Turchetta  et al.: APVD, Proceedings of the 3rd Workshop on Electronics for the LHC experiments, London, 22-26 September 1997; 2 Ph.Schmitt et al.: APVD, Proceedings of the 4th Workshop on Electronics for LHC Experiment, Rome (Italy), 20-24 September 1998; 3  M.Raymond et al.: APV6, Proceedings of the 3rd Workshop on Electronics for the LHC experiments, London, 22-26 September 1997, and references  therein;  4  C.Hu-Guo et al.: APVD_AC and APVD_DC, Proceedings of the 5th Workshop on Electronics for the LHC experiments, Snowmass, 23-27 September 1999; 5  to be published 02004006008001000120014001600180020000 5 10 15 20 25I leakage = 0  µAI leakage = 3.1 µAI leakage = 6.2 µAI leakage = 10.9 µApFENC in Peak mode

The APVD readout circuit for DC-coupled silicon detectors

The APVD readout circuit for DC-coupled silicon detectors

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