The processing of analog information is always spoiled by additional DC level and noise given by the sensors or their additional readout electronics. The Dilogic-2 ASICcircuit has been developed in a 0.7um n-well CMOS technologyto process the data given by Analog to Digital Converters, in order to eliminate the empty channels, to subtract the base line (pedestal) and to locally store the true analog information.(Abstract only available, full text willfollow

Martinengo, P

Santiard, Jean-Claude

Witters, H

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DILOGIC-2 a Sparse Data Scan Readout ProcessorFor the HMPID Detector of ALICEH. Witters, IMEC vzw , 3001 Leuven, Belgium (witters@imec.be)J.C. Santiard , CERN 1211 Geneva 23, Switzerland (jean-claude.santiard@cern.ch)Paolo Martinengo, CERN 1211 Geneva 23, Switzerland (paolo.martinengo@cern.ch)AbstractProcessing of analog information is always spoiled byadditional DC level and noise given by the sensors ortheir additional readout electronic. The Dilogic-2 circuithas been developed to process the data given by anAnalog to Digital Converter in order to eliminate theempty channels, to subtract the base line (pedestal) andstore locally the true digitised information. The analoginformation will be sent to the ADC by a set of three 16-channel front-end analog processors, the Gassiplex07-3[1], multiplexed on the same analog line.I. INTRODUCTIONThe Dilogic-2 can handle up to 64 channels by groupof 16, 32, 48 or 64 channels. The processing has to bedone in two steps, firstly pedestals and noise of eachchannels have to be measured and stored on the chip, thenthe normal operation can start, zeros will be eliminatedand the on-chip memories will be loaded with true valueinformation. The sparse data scan section is made of adigital comparator and a subtractor; the pedestal field hasbeen limited to 8-bits while the data have 12-bits range.These two elements are fed on one side by the digitisedinformation and on the other side by the contents of twoseparate memories filled respectively for each channel bythe chosen level of comparison (threshold) and thepedestal value. Calling PED(i) and SIG(i) the average andr.m.s. values of a pedestal distribution, the operatingthreshold of the channel (i) is defined as: TH(i) = PED(i)+ N*SIG(i), where N is a selectable constant, usually t3.Thresholds and pedestals are first measured and stored ina memory, for every channel; the channel address allowsfinding the right values of each channel during theprocessing. A BIT-MAP memory (64w x 16-bits) is filledwith “1” for channels above threshold or “0” for channelsbelow the threshold. An analog data FIFO memory (512wx 18-bits) is loaded with the digitised amplitudeinformation (12-bits) and the address of the selectedchannels (6-bits). An End-Event word turns off the eventreadout sequence; it contains the number of goodchannels (7-bits) and the corresponding event number(11-bits). A presettable almost-full flag indicates over-writing the FIFO and an internal 4-bit controller allows tochoose the different front-end and back-end operations,particularly one, which is used to test the functionality ofthe chip.Finally, the Dilogic-2 can be daisy-chained to allow thereadout of several hundreds of channels on the same bi-directional data bus at a maximum speed of 20MHz witha power consumption of 60mW.The Dilogic2 is divided into three main parts: the front-end that concerns the writing part of the circuit, the back-end with the memories and the different flags and finallythe controller. Fig. 1 shows the layout and Fig. 11describes the block diagram of the Dilogic2.Fig. 1: Dilogic2 layoutII. CONTROLLERThere are two main operations that can be performedsimultaneously if necessary: the front-end operation andthe back-end operation.The front-end operation reads digital information, in ourcase from an ADC, makes the necessary calculations andstores the data into the memories.The back-end operation is connected to an externalprocessor through an 18-bits bi-directional bus.The controller can instruct the Dilogic2 to performseveral operations under the control of the externalprocessor. Table 1 shows the functions that have beenimplemented and can be activated with a 4-bit code.Table 1: 4-bit Function codeFunction code              Description000000010010…011110001001101010111100110111101111Front-end test modeLoad “almost full” presetNo operationPattern readoutPattern deleteAnalog readoutAnalog deleteReset fifo pointersReset daisy chainConfiguration writeConfiguration readIII. FRONT-END OPERATIONA. Data AcquisitionX X XX X XTrgClkClr_NAmplChAddrX XX X XX X X X X1 2 3 n-1 nFig. 2: Data acquisition timing diagramFig. 2 shows that, before starting the first acquisition ofdata the front-end has to be cleared with Clr_N and theback-end with Rst_N. Then the subtraction memory andthe threshold memory have to be filled respectively withthe pedestal value and the operating threshold of eachchannel, namely PED(I) and TH(I) = PED(I) + N*SIG(I).The SubCmp pin allows disabling the subtractor and thecomparator during the pedestals and the noisemeasurements.Every event starts with a pulse on Trg and a number ofclocks on Clk that will depend on the number of channelsto be processed by group of sixteen. It is defined by a 2-bit code shown in Table 2.Table 2: Write clocks Vs number of channelsNrofGx Nb. of input data     Nb. of clocks00 16              1701 32 331011              48              644965When the SubCmp is in the low state (disable), theamplitude Ampl and channel address ChAddr are put inthe data fifo memory without subtraction of the offset.When the SubCmp pin is high (enable) the data are onlystored if the amplitude is bigger than the threshold. Thedata stored in the DfifoRam is the amplitude minus theoffset and the corresponding channel address.The pattern word, in every event, can be 1, 2, 3 or 4groups of 16 bits depending on the number of channels.They are stored in the BIT-MAP memory. Every bit ofthe pattern word indicates whether or not (1 or 0) a hit hasoccured on that channel.An extra clock cycle is necessary to store the end-eventword and turn off the readout of an event. The 18-bits ofthe end-event word are the contents of 2 counters: 7-bitsfrom D00 to D06 give the number of channels above thethreshold and 11-bits (D07-D17) give the eventsnumbering. The end-event word is signalled in time bythe Mack-N output.B. Test modeFig. 3 shows the test mode operation, which is similar tothe data acquisition sequence, but instead of asserting theamplitude and channel address on the input pins, theyshould be filled through the I/O bus, respectively withChAddr (5:0) on D17-D12 and Ampl (11:0) on D11-D00.XTrgClkClr_NAmplChAddrX XX X X1 2 3 n-1 nFCode 0000StrIn_NXXData X XX X XXFig. 3: Test mode timing diagramIV. BACK-END OPERATIONMost of the operations defined by the function code(Table1) are made in the Back-End mode. We willdescribe the main functions.A. Almost-Full pre-set load FCodeStrIn_NData XX0001DFig. 4: Almost-full pre-set timing diagramThe load pre-set operation (Fig. 4) loads a register in thedata fifo controller with a 9 bit value, D08-D00.This number is used to compare the read and writeaddress counters. The pin AlmostFull_N goes low whenthe write counter value reaches the read counter valueminus the loaded pre-set.  This flag indicates that the datafifo is almost full, and should be used to stop the triggerflow in order to prevent overwriting. If the pre-set is notloaded, the pre-set register defaults to 67 after reset of theDilogic2 chip.B. Analog readoutFCodeStrIn_NEnIn_NDataEnOut_NXZ X X X1010 1101D D D EDataMAck_NEnd-event wordEmpty_NNoAData_NZFig. 5: Analog readout timing diagramThe Dilogic2 chip is put in analog readout mode (Fig. 5)when the function code is set to”1010” and EnIn_N islow.Successive StrIn_N cycles will cause all modules in thechain to place their digitised data on the data bus one at atime, starting with the first module in the chain. Anenable signal is passed from the EnOut_N pin to theEnIn_N pin of the next chip when the module hasfinished putting its analog data of one event on the databus.The Mack_N pin indicates the occurrence of the end-event on the data bus and marks the end of the analogreadout on that Dilogic2. At that moment the EnOut_Npin is pulled low to start the readout of the next chip, andMack_N goes high again.The analog readout operation is finished when theEnOut_N of the last chip goes low.All the Dilogic2 have to be reset by applying the resetdaisy chain code “1101” and an extra Strin_N strobe. Thiswill reset the EnOut_N pins of all chips in the chain,otherwise they will stay in analog readout mode.The analog data fifo has 2 flags: the Empty_N flagindicates that the fifo is completely empty and theNoAData_N indicates that there is no analog informationin the fifo, but only end-event words. This status occurswhen the Dilogic2 has received triggers with emptyevents. The function code allows deleting the events inthe fifo, starting with the first event to be read.C. Pattern readoutThe Bit-Map memory stores the profile of an event bywriting “1” or “0” if the amplitude on the channels havebeen bigger or not than the threshold.Channels status is stored with words of 16 bits, thus oneword per 16 channels from  D00 to D16.FCodeStrIn_NEnIn_NDataEnOut_NDataEnOut_NDataEnOut_NDataEnOut_NZZZZZZZZXX XX X X1000 11011 Gassiplex chip2 Gassiplex chips3 Gassiplex chips4 Gassiplex chipsDD DD D DD D D DXXXXFig. 6: Pattern readout timing diagramTo perform the pattern readout (Fig. 6), the function codemust be set to “1000” and EnIn_N must be low. Thepatterns will appear on the data bus as long as StrIn_Nremains low.The readout sequence will be the same as the analogreadout, it will be finished when the last module drives itsEnOut_N pin low. A reset daisy chain has to be applied toturn off the EnOut_N pins.As in the analog readout mode a pattern delete can beperformed.D. Configuration writeThe threshold and offset memory can be loaded (Fig. 7)using the function code “1110”, EnIn_N set to low andStrIn_N cycles. The data should be stable on the data busat the rising edge of StrIn_N.The first 64 cycles of StrIn_N are used to write the firstDilogic, after which it asserts its EnOut_N low and enablethe next chip which will take the next 64 cycles to load itsdata.A reset daisy chain has to be applied at the end of theoperation.FCodeStrIn_NEnIn_NDataEnOut_NXX X X X1110 1101D D D D1 2 63 64Fig. 7: Config. write timing diagramE. Configuration readThe threshold and offset memory can be read back (Fig.8) using the function code “1111”, EnIn_N set to low andStrIn_N cycles. The data will appear on the data bus afterthe falling edge of StrIn_N and will stay stable until therising edge of StrIn_N. 64 StrIn_N cycles have to beapplied to read each Dilogic and the reset of daisy chainhas to be applied to end the operation.FCodeStrIn_NEnIn_NDataEnOut_NZZ X X1111 1101D D D D1 2 63 64XXFig. 8: Config. Read timing diagramF. Reset fifo pointerUFCodeStrIn_N1100U ZMAck_NEmpty_NNoAData_NAlmostFull_N ZData U ZUUEnOut_N UFig. 9: Reset fifo pointer timing diagramWhen function code “1100” is applied (Fig. 9), theaddress counters in the data fifo and bitmap fifo memoriesare reset after a StrIn_N cycle is given. The result is amemory clear.G. Reset daisy chainBy applying “1101” or “0xxx” to Fcode and a StrIn_Ncycle, the Dilogic2 will set the state machine that controlsthe back-end, in the start state (Fig. 10).It has to be used at the end of the following modes:pattern readout, analog readout, configuration write,configuration read.The state of the following pins will change: EnOut_N willbe set high while Mack_N and the data bus will be put intri-state.FCodeStrIn_N1101U ZMAck_NData U ZEnOut_N UFig. 10: Reset daisy chain timing diagramV. CONCLUSIONSThe Dilogic2 has been tested successfully by loadingrandom data on the front-end at a rate of 10MHz. Noerrors have been detected after performing the sparse datascan operation and readout of the analog memory and thebit-map memory at the same clock cycle.To simplify the analog front-end electronics by removingthe Digital to Amplitude Converters that were supposedto adjust the offset between the Gassiplex, we have beenasked to increase the subtraction and threshold field to 9bits instead of the present 8 bits. The new version will beavailable in the beginning of 2001.The Dilogic2 is an upgrade of the Dilogic1 that had beendesigned to be used with an 8-bits 4 ranges ADC. Thisfirst chip had been the implementation in a full ASIC ofthe sparse data scan part of a CAMAC module, theDRAMS [2].VI. REFERENCES[1] J.C. Santiard, K. Marent, The Gassiplex07-2Integrated front-end analog processor for the HMPID andthe Dimuon spectrometer of Alice.[2] E.Chesi et al., Nucl. Instrum. Methods A283 (1989)602Fig.11:Dilogic2 block diagram

Dilogic-2: A Sparse Data Scan Readout Processor for the HMPID Detector of ALICE

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