Atkin, E

Mishin, Yu

Volkov, Yu

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ANALOG SIGNAL SPLITTERE.Atkin, Yu.Mishin, Yu.Volkov, Moscow Engineering Physics Institute, Russiae-mail: atkin@eldep.mephi.ruAbstractThe high-speed (wide-band) splitter circuit forreading out photomultiplier analog signals is described.The splitter can simultaneously drive loads of the type ofCFD, LED, ADC, QDC, TDC and so on.The photo of the manufactured prototype printedcircuit unit (PCU), based on microwave transistors andfitted with LEMO connectors, is presented. Thedimensions of the 4-channel PCU are 75*50 mm.sq. Thesplitter provides a high slew-rate of about 2000 V/us,large dynamic range up to 60 dB and low powerconsumption 250 mW.1. INTRODUCTIONA number of LHC experiments (for instance,ones with time-of-flight detectors) require high-speed(wide-band) splitters of photomultiplier analog signals.The splitters should have a high slew-rate (up to 2000V/us), large dynamic range (up to 60 dB) and low powerconsumption (tens of mW). The main destination of thesplitters is to provide simultaneous parallel signalprocessing by amplitude, charge, time and so on. Thesplitter can drive loads of the types of CFD, LED, ADC,QDC, TDC and so on.2. STRUCTURE AND SCHEMATICSThe most  acceptable  circuital  solution in thecase of both polarity pulses is the use of  push-pull ABstages with complementary microwave bipolar transistors.The elaborated splitter circuit contains an inputsection (core) and output buffer stages, as shown inFigure 1.Input section (core) --current feedback ampOutput buffer #1Output buffer #2Output buffer #NFigure 1. Structure of the splitterThe core is built according to the currentfeedback  schematics.  It is responsible  for bandwidth,static  parameters (input offset voltage and inputcurrents).  The latter set a limit to the dynamic range.Taking  into  account  disturbances,  cross-talks  and  thestandard  offset  voltage  for  a  pair  of  bipolartransistors  to  be  ~1..2 mV,  one  should  assumeminimal  input  signals  of  ~5..10 mV.  Therefore inorder  to  provide  60 dB  of  dynamic  range  there  mustbe  ensured  a  maximal  output  amplitude  not  lessthan 5V.Moreover the core provides the limitation of theoutput voltage swing by a value of about 6V, therebyprotecting the output stages from burnout. This isprovided by applying a nonlinear local feedback to thecore.The  output  buffer  stages  (compound  voltagefollowers)  provide  driving  low-ohmic  loads  (astypical  – 50 Ohms each).  The  value of fan-out (numberof  output stages operating in parallel), can vary from 1to 6 depending on the total load.Simplified  schematics of a single splitterchannel is shown in Figure 2.Figure 2.  Simplified schematics of the splitter channel3. IMPLEMENTATION AND LAB TESTS3.1 Prototype UnitThe views of the manufactured prototype printedcircuit unit (PCU), based on microwave transistors andfitted with LEMO connectors, are shown in Figure 3. Thedimensions of the PCU are 75*50 mm.sq.Figure 3. Views of the prototype splitter unitThe circuit indeed has determined the structureof the PCU as a multiboard one. The output sectionsthereat have been designed mechanically in the manner ofa bookstand and connected by their input terminals as awired-OR. This allows to extend simply the fan-out.Two versions of boards have been elaborated:· based on transistors, packed in SOT-23.Both transistor types (npn- KT3130 andpnp- KT3129 ones) have ft somewhat above300 MHz;· based on caseless matched transistor pairs,having ft exceeding 1 GHz for the npn-transistors KTC398 and exceeding 500 MHzfor pnp- ones KTC393.In the capacity of output transistors in both casesthere have been used more powerful npn- transistors ofthe type KT642 (ft~5 GHz at Imax=120 mA) and pn-ones of the type KT658 (ft~3 GHz at Imax=100 mA).3.2  Lab Test ResultsThe prototype PCU provides operation at a unitygain and a fan-out of 4 at load resistances of 50 Ohmeach. The maximal output amplitude thereat makes up atleast 5V. Rise/fall times are within 2.5 ns. Signal polaritycan be any. The maximum rate is not less than 200 kHz.Offset voltage for each output does not exceed ±3 mV.This is achieved at the expense of including trimmerpotentiometers in  the circuit at the stage of adjustment.At supply voltages of ±10V power consumptionis 250 mW/channel. Considering the high speed  and bandwidth(above 100 MHz), along with circuital matters muchattention should be paid to mechanical designimplementation. Therefore circuit simulation and PCBrouting were done taking into account the influence of thereactances of PCB conductors and pads on the electricparameters.3.3  Outlooks for IC designingAt present the task of miniaturizing the splitter isbeing solved. It is expected to implement the testedcircuitry in the form of a semicustom IC. It is planned  tosupplement the circuit with a gain control for separatesplitter outputs and an electronic adjustment of DC outputpotentials, aimed at setting them as close to zero aspossible.4. ACKNOWLEDGEMENTSWe acknowledge the helpful discussions withUli Thoering from Uni. Giessen and Romain Holzmannfrom GSI (Darmstadt),  who gave the start of the splitterdevelopment.Also we thank our colleagues from SRIPT(Moscow) for manufacture of the prototype boards.The work is supported by the InternationalScience and Technology Center (ISTC).

Analog Signal Splitter

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