Caponetto, L

Lo Presti, D

Randazzo, N

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CHARGE AMPLIFIER AND ANALOG MEMORY FOR SILICON DRIFTDETECTORS IN ALICENunzio RANDAZZO , Domenico LO PRESTI and Luigi CAPONETTO(e-mail: randazzo@sunnr.ct.infn.it)University of Catania and INFN Sez. CataniaCorso Italia,57 I-95129 CATANIA - ItalySUMMARYAccording to our simulations [1], a preamplifier-shaperhas been designed. It has 8 channels. Each channelconsists of a charge preamplifier and a CR-RC shaper tolimit noise. Thermal and shot noise has been simulated as300 e-. Since the foreseen leakage current is not more than10 nA, the preamplifier has a sensitivity of 155 mV/MIP, inorder to achieve the assigned 7 Mip range. The shaperhas a gain of 1 V/V and a driving capability of 7 pF asrequired by the 256-cell Analog Memory.A 16 channels 256 cells analog memory has been realisedas a switched capacitor array. It works as an analog delayline. The read frequency is 1 MHz driving 15 pF outputload and the write frequency is 40 MHz. This device hasto be tested. A previous prototype (64 cells 4 channels)working at the same write and read frequency showedduring tests the expected performances. Dynamic Range3.5 V Dc gain 0.9988.CHARGE AMPLIFIERAnalog front-end has been designed with a traditionalscheme, as shown fig. 1. It consists of an integrator and aCR-RC shaper plus an output buffer to drive the analogmemory.Both preamplifier and shaper stages are based on a single-ended folded cascode as shown fig 2. This solution offersbetter performances in term of stability and gain comparedwith standard cascode [2] . For preamplifier stage a choiceof PMOS input transistor was addressed  for better resultin term of flicker noise.Accurate noise analysis was performed to sizing inputtransistor taking into account detector capacitance andpower dissipation. Coupling capacitor of 20 pF wasimplemented inside the chip.Main characteristics are:Table 1      Amplifier Simulation ResultsNoise < 500 e-Input range 7 MIPOutput range 1 VSensitivity 155 mV/MIPShaping time 55 nsDriving capability 7 pFPower dissipation 2.2 mW ABSTRACTIn Silicon Drift Detector front-end the signals coming from each anode of the detector are sent to one input of a Preamplifer-Shaper  whose outputs are connected to the inputs of an Analog Memory (AM). The AM continuously samples the analogsignals at 40 MHz (the bunch-cross rate) and stores all the data. When some suitable conditions are detected, a triggersignal stops the write phase. Then a read phase begins to transfer, at lower rate (1 MHz), the data to another device thatperforms digitalisation.Figure 2 Schematic diagram of core amplifierAmplifier test resultsA 8-channels amplifier has been realised in 0,8 micronAMS CMOS technology. Test results agree withsimulations results showed in Table 1. We have someproblem with noise performance that is worse comparedwith simulations, probably due to the parasitic effects ofthe coupling capacitance at the input of the preamplifier.Figure 4 shows  measured output transient responses ofthe amplifiers .This work suggests a new solution for DC couplingamplifier with the compensation of the leakage current.ANALOG MEMORYWe have designed different prototypes of the ADeLinefamily Analog Memories. In this section we merelydescribe the characteristics of ADeLine4 and ADeLine5chips.Table 2 ADeLine summarises family main characteristics.Table 2 ADeLine FamilyChip nameCh.n°Cell xch.Tot.CellsResolution TestedADeLine1   8    256 2048 Not working    *ADeLine2   1       8   8      <1 mV    *ADeLine3   3      64  192      6 mV    *ADeLine4   4    256 1024     < 1 mV    *ADeLine5  16    256 4096   Not avail.    *ADeLine6  16    256 4096   Not avail. Not avail.Within the overall system, the Analog Memory operatesas an analog delay line, sampling the voltage at its inputsat 40MHz rate and storing its values for each channel in aswitched capacitors array. This array acts in parallel as acircular memory rewriting new samples over the cells whenthe overall channel depth has been reached.Each channel uses an output buffer for the readout of thestored samples. The maximum rate of this phase is 1MHzbecause of power dissipation constraints.The Control Unit simply selects cells in a sequential wayat different rates for the write and the read phase. Thisunit consists of a ring shift register whose outputs linesare fed into one input of an array of two inputs AND cells.The other input of the AND cells of this array is aninternally generated validating “enable” signal (Figure 5).The purpose of this "and" array is to guarantee a nonoverlapping addressing scheme for all cells along thechannel. Two different feed control signals are usedduring the write and the read phase: while in the writephase it is a fixed 50% duty cycle 40MHz system clock, anexternal acknowledge-based mechanism is used in theread phase. The digitizing device, following the memory inthe read-out chain, requires next cells data wheneverready, while memory reacts with a valid data signal. Thatscheme goes on until all memory cells are read.Figure 3 Microphotograph of the chipFigure 4: Amplifier measured output responseFigure 5. Analog Memory overall structureMain design constrains for the memory as well as for thewhole system has been power dissipation and resolution.Memory DesignADeLine5 memory chip is an analog full custom VLSIASIC designed in AMS 0.8m  CMOS 2 metal/2 polyprocess. Its sizes are 3,3x3,6 mm2.The design of the sampling capacitors has been carefullystudied to achieve the best matching in order to have highresolution. Dummy capacitors structures was implementedas well.The memory cells structure (Figure 6) has been designedfor a sampling period of 25ns because of the expectedinput signals whose rise time exceed 50 ns. This factimposes an upper constraint to the size of capacitors andinput switches size while technology and matchingconsiderations impose a lower constraint.The output buffers use folded cascode transconductanceamplifiers for the readout of the selected cell together witha 3 switches configuration.The design of the digital control part is completely static,advantaging of the low-power characteristics of CMOSgates design. A binary tree clock distribution scheme wasimplemented as well.Mixing on the same chip digital and analog parts hasconduced to an accurate grounding scheme to avoidunwanted signals coupling that worse resolution.Memory simulation and test resultsTests have been performed on ADeLine4 and ADeLine5chips. They show a resolution of 10 bit with a noise of0.821 mV  in a voltage range of 3.5 V.The new ADeLine5 chip is a 256 cells 16 channels analogmemory and it is currently under test but preliminaryresults are it similar to the ADeLine4 chip tests.A new chip, ADeLine6, has been designed and sent to thefoundry: it will be available at the end of November. It hasthe same characteristics of ADeLine5 but a new standardcells control unit has been added. To reduce the externalsignals needed generates the acknowledge signals insidethe chip.CONCLUSIONSTest measurements show that both preamplifier andanalog memory need some adjustments to fit theexperimental requirements. Anyway their measuredperformances are quite near to specifications.The next step will be a chip containing both preamplifierand analog memory in order to test the whole electronicchain.REFERENCES[1] C.Petta, U.Becciani, G.V.Russo, “Simulation andcharacterisation of the front-end of SDD in ALICE ITS”,Proc. of 4th LHC Electronics Conf., Rome, 21-26 Sept. 1998,pp.610-614[2] M. Ismail, T. Fiez – Analog VLSI – Mc Graw Hill[3] S. Panebianco et al. “Switched capacitor arrays analogmemory for sparse data sampling”, to be published inNuclear Instruments and Methods in Physics Research.VaVbCj1 Cj2Sej+-Cj256SrtjSrbjSwtjSwbj Sj1 Sj2 Sj256VojVij top linebottom lineFigure 6: Single ADeLine channel simplified schematic.Figure 6 ADeLine5 chip microphotography

Charge amplifier and analog memory for silicon drift detectors in ALICE

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