Kloukinas, Kostas C

Marchioro, A

Moreira, P

Placidi, P

CERN Document Server

A 40 MHz clock and trigger recovery circuit for the CMS trackerfabricated in a 0.25 m CMOS technology and using a self calibrationtechniqueP. Placidi1, A Marchioro2, P. Moreira, K. KloukinasCERN/ECP, CH-1211 Geneva 23, SwitzerlandABSTRACTIn the CMS central tracker, the LHC clock and thefirst level trigger decisions are distributed encoded as asingle signal. This paper describes an ASIC for clockrecovery and first level trigger decoding to be used in thetracker data acquisition and slow control systems. The ICwas implemented in a 0.25 Pm CMOS technology using arad-tolerant layout. It recovers the clock and triggersignals meeting the CMS tracker power budget andradiation hardness constraints. In the design of this ASICa self-calibration techniques was adopted toaccommodate for process parameters spread and deviceparameter changes due to radiation induced damage.1 INTRODUCTIONThe CMS central tracker electronics operatessynchronously to the 40.08 MHz LHC master clock. Inthis system, the clock and the first level trigger decisionsare encoded and distributed as a single signal as shown inFigure 1.CLK_T1T1CLK~ 25 nsENCODERFigure 1 Clock coding schemeThis signaling scheme minimizes the bandwidth andthe power requirements of the transmission system.However, a dedicated circuit is required to recover theclock and the trigger signal in the front-end and controlmodules (Figure 2). The recovered clock is used in thefront-end APV ASIC for data sampling and thereforejitter less than 0.5 ns is required to maintain the precisionof the analog measurements. As the circuit has to be usedin an environment close to the sensitive analogue front-end electronics, it is necessary to reduce the switchingnoise generated by the IC. Moreover, this circuit has tooperate in an environment where, due to the large numberof readout channels, the power consumption has to beminimal. Finally, the central tracker is a detector regionthat exhibits severe radiation conditions [1, 2]. It is thusrequired to guarantee a total dose tolerance that can be ashigh as 10 Mrad over a period of 10 years.To meet the requirements described before and thetracker radiation constraints, the IC has been implementedusing radiation tolerant layout techniques [3] in a 0.25 PmCMOS technology.APVsCLK T1MUXLASERDRIVERPLL DelayDETECTORFRONT-ENDMODULEPLL-DelayCLK_T1CCUCLK_T1CLK_T1DINResetDOUTNEXT CCUPREVIOUS CCUI2 C- SCL(x12)I2 C-SDA(x12)CLKReset···CONTROL MODULE·Reset·Figure 2 The PLL-Delay IC as used in the front-end andin the control modules of the CMS tracker2 PLL-DELAY CHIP ARCHITECTUREBesides the clock recovery and trigger decodingfunctions, mention before, the developed ASIC (PLL-Delay IC) implements phase deskewing for the clock andtrigger signals. The clock phase can be adjusted in stepsof 1.04 ns (fine deskew) up to a maximum delay of 25 ns,while the trigger signal phase can be delayed up to amaximum of 16 clock cycles also with 1.04 ns resolution.The major blocks of the ASIC are shown in Figure 3,they consist of: a 40 MHz Phase-Locked Loop (PLL), atrigger decoder, a programmable delay line, a calibration1 On leave from INFN and University of Perugia, Italy2 e-mail: Alessandro.Marchioro@cern.chstate machine and an I2C interface that allowsprogramming various parameters in the IC internalregisters.Trigger  DecoderDelayLineI2CSlaveInterfacePLLSCLSDACLKI2C_AddT1CLK_T1CalibrationState-machineFigure 3 PLL block diagramThe core of this ASIC is the PLL [1,3, 4]; it consistsof the following major blocks:- a double mode digital phase detector, working,during the lock acquisition, as a 3-state PhaseFrequency Detector (PFD) and, once lock isachieved, as a 2-state Phase Detector (PD);- a charge-pump circuit, converting the signals fromthe PFD/PD into a control current. The charge pumpcircuit consists of two 10 PA current sources and fourswitches controlled by the phase detector outputs;- a loop filter integrating the charge-pump current andcontrolling the loop dynamics.- a 12 stage differential Voltage Controlled Oscillator(VCO). To ensure proper power supply noiserejection and also to minimize the generated noise, adifferential constant amplitude VCO, similar to theone described in [3], was used. Each stage is acurrent–controlled differential delay cell. Tooptimize the jitter behavior of the VCO, a linearrelationship between the VCO control voltage andthe VCO frequency was implemented. The signalamplitude of the VCO cell is held constant by meansof a replica bias circuit and a power supplyindependent reference generator.As shown in Figure 4, clock phase shifting isimplemented by selecting the output of one of thetwelve VCO stages using a multiplexer.Two conflicting requirements exist in the design of alow jitter PLL. On one hand the smallest possible PLLgain is desirable to ensure the lowest possible jitter in thepresence of input noise and of suppressed clock cycles.On the other hand, to cover the whole range of processand temperature variations a high loop gain is necessaryto ensure locking. Phase noise filtering is one of the majorgoals of this design and, consequently, a low loop gainPLL was implemented. In the IC process chosen and withthe required low loop gain, it is not possible to guaranteephase locking under all conditions. To circumnavigatethis problem a digital circuit implementing an auto-calibration procedure was implemented. This calibrationprocess (to be described later) compensates also forprocess parameter spreads and device parameter changesdue to radiation damages.VCOBuffersMUXDouble-to-SingleEnded Converter0            11            1                     9                          5                624 : 2CECE SelectorOUTPUT CLOCKFigure 4 Representation of the clock delay selection2.1 SYSTEM STABILITYThe loop filter consists of a series, resistor/capacitor inparallel with a smaller capacitor. This last capacitor, isadded to mitigate the frequency ripple of a second orderloop. It introduces an additional pole in the PLL openloop transfer function/b)2sT(12s2T)2sT(1cw(s)0G (2)where, wc=KVCOIpR(b-1)/2Sb, KVCO is the VCO gain,b=(1+C2/C1), Ip the charge pump current and T2=R C1.1001011021032030405060708090bPhase margin (degree)Z 72124=cNOMINAL CONDITIONSFigure 5 Phase margin of the loop as a function of bparameter. The gray area delimits the variation region ofthe parameters.The location of this additional pole must be chosen insuch a way that the steady state and the dynamic responseshould stay practically unchanged. In addition, thepresence of this pole has to be chosen to guaranteestability. By inspection of the Bode diagram it wasverified that for the chosen design parameters the stabilityof the system is maintained over the entire range ofprocess parameters, power supply voltages andtemperature.In Figure 5 the phase margin as a function of b withwcT2 as parameter is shown. For small values of b thephase margin becomes small indicating a poorly dampedsystem with a conjugate pole pair close to the imaginaryaxis.2.2 NUMERICAL MODELPhase Locked Loop circuits are difficult to simulate atthe circuit level. The complexity of the complete ASICand the long time required for the PLL to achieve lock(several microseconds of real time) typically demandsprohibitively long computing time (> 24 hours) with toolssuch as Spice. Therefore, a behavioural discrete timemodel of the PLL has been implemented allowing quickstudy of the system design space and optimization of thecritical circuit components. A model has been developedand coded in C.    0  501001502002503003500        1        2       3        4       5        6        7       8Time (msec)Figure 6 Simulated PLL jitter when a trigger pulse occursThe system stimulus can be chosen clean or noisy tostudy the low frequency noise filtering properties of thePLL. Random triggers, i.e. missing clock pulses, can alsobe programmed in the clock sequence to simulate realLHC conditions. The simulated response to a missingclock pulse is shown in Figure 6 when filter parameterscorresponding to the actual implementation are used inthe simulation model.2.3 AUTO-CALIBRATION PROCEDURETo accommodate for process variations and devicesparameters changes due to radiation damage an auto-calibration procedure has been implemented. In Figure 7-(a) it is represented a typical relation between the VCOfrequency range and the loop filter voltage. In Figure 7-(b) it is represented the type of transfer characteristicsimplemented in this design. The VCO has a small gain(KVCO) and its operation frequency is a function of thePLL control voltage (Vc) and of an offset current (Ip) suchthatfVCO= KVCO Vc + f(Ip).As can be seen in the picture only some of the curveswill allow the PLL to lock at the required 40.08 MHzfrequency. Therefore at the start-up (or each time a resetis received) it is necessary to select the suitable lockingrange. To do this the calibration procedure shown inFigure 8 is executed.The offset current (Ip) of the VCO delay cell isinitially set to a minimum value (Ip0) and the PLL isallowed enough time to lock.VCfVCOVDDVDD/2Ip0Ip n-1Ip nIp n+1Ipmaxfmaxfmin High Gain Low Gain040 MHzVCfVCOVDDVDD/2fmin040 MHz(a) (b)Best conditionsNominal conditionsWorst conditionsFigure 7 (a) Typical VCO characteristic when powersupply, temperature and process variations areconsidered; (b) implemented VCO characteristicIf the lock is not achieved this means that the VCO isin one of its characteristics curve (Figure 7-b) that doesnot cross the operation frequency and, consequently lockmight not be possible. In this case the offset current isincreased and the whole process repeated until the circuitis able to acquire lock at the right frequency.In the case the offset current is set to the maximumvalue (Ipmax) and the lock is not achieved, the PLL gain isincreased (High Gain mode) and the calibration sequenceis started again.Ip= Ip0Ipn=Ipn-1+1WaitNOIpn<IpmaxLockachievedNOIp[n]=Ip[max]YESIpn<IpmaxHigh GainIpn=Ipn-1YESIpn=IpmaxHigh GainEndCalibrationPower-onor ResetCalibrationfailedFigure 8 State transition graph for the autocalibrationprocedureOnce the lock is achieved the phase detector - whichup to now has been operating in the phase-frequencymode - is switched to the phase detector only mode.The auto-calibration process is stopped and all theASIC functions are enabled.3 IMPLEMENTATIONThe IC has been submitted for fabrication using a 0.25Pm CMOS technology (Table 1) and implemented usingrad-tolerant layout techniques [5, 6].Radiation tolerance of integrated circuits is a primaryconcern in future high-energy physics experiments.Prototype version in 0.8 Pm Prototype version in 0.25 PmBiCMOS, 2 level of metal,2 polyCMOS, 3 level of metal,1 polyPower supply=4 V Power supply=2.5 VArea Chip core = 1.6x1.3 mm2Area Standard Cell = AArea Full custom part = AcArea Chip core = 0.9x0.8 mm2Area Standard Cell = A/8Area Full custom part = Ac/2Available Submitted for fabricationTable 1 Technology featuresAlthough radiation hard technology exists, they do noalways provide:- adequate density;- high volume, high yield and low cost per wafer.In addition, in a deep submicron technology justbecause the power supply scales down the powerconsumption decreases.On the other hand the ultra thin oxide of deepsubmicron technologies is inherently tolerant to total doseeffects reducing significantly the radiation-inducedchanges of transistors parameters. Moreover, byemploying enclosed geometry and P+ guard-rings aroundN-channel devices the radiation-induced leakage pathsalong the edge of the devices and between devices areeliminated.Figure 9 PLL-Delay prototype layoutSimulations and experimental results on test structuresdemonstrate that the use of standard static architecturesshould be robust enough not to experience a significantrate of Single Event Upset (SEU) in LHC [7].Recent results have confirmed the potential of thisapproach, and have demonstrated design solutions in deepsubmicron technology that minimize total dose effectsand the risk of Single Event Upset (SEU).A previous prototype version of this IC was fabricatedin a commercial 0.8 Pm BiCMOS technology [8],resulted in an area of 2.6x2.1 mm2, where roughly half ofthe area was used by digital standard cells. In this newversion (Figure 9) the area occupied by the digitalstandard cells has been reduced by a factor of 8 while thefull custom part is reduced by a factor of 2. Moreover,due to the reduction of power supply voltage the powerconsumption has been reduced by about 40 %.4 CONCLUSIONSA PLL-Delay ASIC for clock recovery and first leveltrigger decoding in the CMS tracker has been designed.The IC has been submitted for fabrication using astandard 0.25 Pm CMOS technology with a rad-tolerantlayout. The ASIC provides a clock signal with adjustablephase in steps of 1.04 ns and a trigger signal with phaseprogrammable in multiples of the clock period. An auto-calibration circuit is used to obtain low jitter avoidingdependency on process and radiation induced damages. Anumerical PLL model was implemented to study thedynamic behaviour of the PLL and to allow optimizationof the loop parameters.5 REFERENCES[1] A.Marchioro et al. “A system for timing distributionand control of front end electronics for the CMS tracker”,Third Workshop on Electronics for LHC Experiment,London, 1997[2] For complete references on the RD12 project, seehttp://www.cern.ch/TTC/intro.html.[3] F. Faccio, Total Dose and Single Event UpsetMeasurements of Test Structures in a Deep-SubmicronTechnology, Fourth Workshop on Electronics for LHCExperiments, Rome, September 21-25, 1998.[4] I. Young et al., “ A PLL Clock Generator with 5 to110 MHz of Lock Range for Microprocessors”, IEEEJournal of Solid State Circuits, vol. SC-27, November1992, p.1599[5] B. Razavi, Monolithic Phase-Locked Loops and ClockRecovery Circuit, IEEE Press, New York 1996[6] G. Anelli et al., Total Dose behavior of submicron anddeep submicron CMOS technologies,[7] K. Kloukinas et al., Development of a radiationtolerant 2.0 V standard cell library using a commercialdeep submicron CMOS technology for the LHCexperiments, Fourth Workshop on Electronics for LHCExperiments, Rome, September 21-25, 1998.[8] P. Placidi et al., A PLL-DELAY Asic for clockrecovery and trigger distribution in the CMS , ThirdWorkshop on Electronics for LHC Experiments, London,September 22-26, 1998.

A 40 MHz clock and trigger recovery circuit for the CMS tracker fabricated in a 0.25 $\mu m$ CMOS technology and using a self calibration technique

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A 40 MHz clock and trigger recovery circuit for the CMS tracker fabricated in a 0.25 μm\mu mμm CMOS technology and using a self calibration technique

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A 40 MHz clock and trigger recovery circuit for the CMS tracker fabricated in a 0.25 $\mu m$ CMOS technology and using a self calibration technique