Cervelli, G

French, M J

Hall, G

Jones, L L

Moreira, P

Morrissey, Q R

Neviani, A

Raymond, M

CERN Document Server

The APV25 Deep Submicron Readout Chip for CMS DetectorsL.L.Jones, M.J.French, Q.Morrissey, A.Neviani, RAL, UK (http://www.te.rl.ac.uk/med/)M.Raymond, G.Hall, IC, UK (m.raymond@ic.ac.uk, g.hall@ic.ac.uk)P.Moreira, G.Cervelli, CERN, SwitzerlandAbstractThe APV25 is a 128 channel analogue pipeline chip forreadout of silicon microstrip detectors in the CMS trackerat the LHC. Each channel comprises a low noiseamplifier, a 192 cell analogue pipeline and adeconvolution readout circuit. Output data are transmittedon a single differential output via an analoguemultiplexer. The chip is fabricated in a 0.25 micronCMOS process to take advantage of the radiationtolerance, lower noise and power, and high circuit densitywhich can be achieved.1.  INTRODUCTIONThe CMS inner tracker contains approximately 107channels implemented in silicon and gas microstriptechnologies, read out by APV chips. For several yearsnow these chips have been developed [1,2] to meet thedemands of low-noise, low power and radiation hardnessrequired for operation at the LHC. More recently it hasbeen demonstrated that commercial deep submicronCMOS technologies currently available may exhibitradiation tolerance to levels in excess of those required[3], together with the possibility of operating with lownoise and power consumption, as well as increased circuitdensity. Because of the potential for improvements wehave embarked on a rapid development programme toproduce a prototype APV chip in a deep submicrontechnology.2.  CHIP OVERVIEWThe APV25 chip has been designed in a 0.25 micronCMOS process and is very similar in concept to previousAPV chips. It has 128 readout channels, each consistingof a 50 nanosecond CR-RC type shaping amplifier, a 192element deep pipeline and a pulse shape processing stagewhich can implement a deconvolution operation toachieve the single bunch crossing resolution necessary athigh luminosity. Analogue output samples are thenmultiplexed onto a single differential output forsubsequent optical transmission to the DAQ system. Theoutput data frame consists of these analogue samplespreceded by a digital header which includes a digitaladdress of the pipeline column from which the dataoriginates. The chip can operate in one of three modes. Inpeak mode, following an external trigger, one sample foreach channel (timed to be at the peak of the amplifieroutput pulse shape) is read from the pipeline andsubsequently output through the multiplexer. Indeconvolution mode, three samples per channel are readfrom the pipeline and combined in a weighted sum beforeoutput. In multi-mode a sequence of external triggersallows a number of consecutive pipeline samples to betransmitted in consecutive output data frames.Figure 1. APV25 chipThe pipeline is used to store the amplifier outputs,sampled at the 40 MHz LHC frequency, while externaltrigger decisions are taken. The pipeline depth allows aprogrammable latency of up to 160 bunch crossings (4microseconds) the remaining locations being used forbuffering of data from up to 10 events (in deconvolutionmode). For technological reasons the pipeline storageelements have been implemented using gate capacitancewhich allows a very dense layout for this memory array.The APV25 deep submicron CMOS chip contains all thenecessary system features, including on-chip bias andcalibration pulse generation, and a slow control interfacefor programming these features and the operating mode ofthe chip. The active chip area is approximately 7.2 x 6.5mm2. However due to its manufacture on a multi-projectrun, the die size is 8.2 x 8.0 mm2.3.  FRONT ENDThe front-end electronics of the APV25 chip areessentially the same as those for APV6, but with slightmodifications to optimise it for the deep sub-micronprocess characteristics3.1 PreamplifierFigure 2. Preamplifier SchematicThe preamplifier is a charge amplifier made from asingle-ended folded cascode amplifier with a 150fFfeedback capacitor. The pFET input transistor has a sizeof  2000 µm / 0.36 µm and is biased at 400µA. Its sourceis connected to GND to reduce power consumption. Theoutput is buffered by a source follower which alsoprovides the level shift required for DC stability throughthe feedback transistor. The feedback transistor alsoprovides a discharge path in order to avoid excessive pile-up in the preamplifier. A switchable unity gain inverter isemployed when detectors of opposite polarity are used toallow full use of the shaper dynamic range (limited by the2.5V power supply). Feed-through is eliminated bypulling the centre of the switches to VSS when theswitches are off. The preamplifier (including the inverter)has a gain of 18.7mV/mip (25 000 electrons) and a powerconsumption of  0.9mW.Figure 3. Response of Preamplifier3.2 ShaperThe shaper is an effective CR-RC filter producing a50ns shaped voltage pulse. The shaping is adjustable,over a limited range, to offset the inevitable degradationof the pulse shape which is caused by irradiation.Figure 4. Shaper SchematicThe shaper  is composed of a single-ended cascodeamplifier (non-folded) with a feedback capacitor of 150fFand a coupling capacitor of  1.4pF. The pFET inputtransistor has a size of 200 µm / 0.36 µm and is biased at48µA. The shaper has a power consumption of 0.25mW,giving a total front-end power consumption of 1.15mW.The total front-end gain is 100mV / mip with a nonlinearity of less than 2% over a 5 mip range.(measured atpoint a in figure 5, corresponding to the third samplet ofthe troplet used in Deconvolution mode).Figure 5. Response of Shaper (Hspice simulation).3.3 NoiseBy far the largest contribution to the front-end noise is theinput transistor of the preamplifier. In simulation, thenoise has been shown to be 246 electrons + 36 electrons /pF. With 18pF of detector capacitance, this gives 900electrons of noise.4. PIPELINEThe pipeline buffers data on-chip for sufficient time forthe level 1 trigger to make a decision. Thanks to thesmaller geometry of the deep sub-micron process thepipeline length could be increased from 160, in previousversions, to 192 thus increasing the maximum latencytime up to 4µs. The FIFO depth (which determines thenumber of triggers which can be reserved for read-out atany one time) has also been increased from 20 to 32.4.1 Analogue MemoryThe pipeline consists of 128 channels by 192 columnsof switched capacitor elements. One side of the capacitorconnects to VSS and the other  to the shaper output busthrough a write switch, and the APSP input bus through aread switch. Due to a limit on the total area of metal-insulator-metal capacitors allowed within the chip, thepipeline capacitor has been implemented using the gate ofa 7 µm x 7µm nFET (280fF). Given the DC operatingpoint of the shaper output, the nFET gate capacitor isalways in strong inversion which guarantees the bestlinearity for voltage to charge conversion.4.2 Digital ControlThe pipeline control sequences the writing, triggering,storing, and retrieval of data from the analogue memory.A write pointer continuously circulates the pipelinesampling the shaper output from each channel at intervalsof 25ns. A trigger pointer follows behind the writepointer, separated by the trigger latency. When a trigger isreceived, depending on the mode of operation, either one,or three columns, marked by the trigger pointer, arereserved for reading out. Once reserved these columnscannot be overwritten until the data have been read out.The column pairing present in previous versions of thechip (due to area limitations) has been removed. Inaddition, the time taken to release consecutively triggeredcolumns in the pipeline, once they have been read, hasbeen reduced. Latency error detection has also beenimproved from previous versions.5. ANALOGUE PROCESSINGSignals from silicon strip detectors arrive at the inputsto the APV25 as single impulses of current which areintegrated in the preamplifiers and then CR-RC shapedinto well defined voltage pulses. These signals are thencontinuously sampled every 25ns, and the samples storedin the pipeline awaiting read-out.In Peak mode one sample is reserved in the pipeline forreading out – this corresponds to the peak voltage of theCR-RC shaped signal. Peak mode is generally used whendata rates are sufficiently low so that the effects of pile-upof detector signals are not significant. In this mode, thesignal-to-noise ratio is maximised and the non-linearity ofthe signal is minimised. However, if pile-up does becomesignificant – at higher rates of data – then to sample justthe peak of the signal is not enough since the CR-RCshaped signals will superimpose. In this situation, the chipis operated in Deconvolution mode.Figure 6. APSP schematicIn Deconvolution mode three samples are reserved inthe pipeline. The third sample corresponds to the voltageat point a shown in figure 5 The second and first samplescorrespond to the voltages 25ns and 50ns (respectively)earlier. In order to determine which 25ns period theoriginal signal occurred it is necessary to deconvolute thethree samples. This operation is performed in the APSP(analogue pulse shape processor).Figure 7. Timing of APSP in Deconvolution ModeThe APSP (figure 6) is a three weight FIR filtercomposed of a charge amplifier and a switched capacitornetwork. It is DC-coupled to the pipeline read bus and sothe operating point of the charge amplifier is matched tothat of the shaper.The operation of the APSP in Deconvolution mode isshown in figure 7. The charge on each of the triggeredpipeline elements is read out, in sequence (during theactive low periods of ri1, ri2 and ri3), integrated onto theAPSP feedback capacitor, and the resulting voltagessampled on the three weighted capacitors. The chargesstored on these weighted capacitors are then summed(during the active low periods of ro1, ro2 and ro3) andagain integrated onto the feedback capacitor which hasnow been increased in size (using last_cycle) to reducethe gain. The resulting voltage is stored on the holdcapacitor during the signal store (active low). This mustbe done while the analogue multiplexer is outputting thedigital header. The DC output level of the resulting signalcan be adjusted using the backplate bias Vadj.Figure 8. Output of APSP in Deconvolution mode.Figure 8 shows the output of the APSP (before the holdcapacitor) operating in Deconvolution mode. If the shapersignal is an ideal CR-RC shape then the first two samplesshould contain no signal. However it can be seen fromfigure 8 that there is a small signal in the second sample.This is due to a slight knee in the rising edge of the shapersignal, and this has been taken into account in theweighting of the APSP capacitors. The gain of the fullanalogue chain up to this point is 100mV / mip with anon-linearity of less than 2.11% over a 5 mip range.Figure 9. Operation of APSP in Peak mode.The operation of the APSP in Peak mode is shown infigure 9. The charge stored in the single pipeline elementis  read out during ri1, integrated onto the APSP feedbackcapacitor and the resulting voltage sampled on the first ofthe weighted capacitor. During ri2, the APSP reset level issampled onto the second weighted capacitor during ri2.The charges stored on these two capacitors are thensummed and integrated on the APSP feedback capacitor(during ro1 and ro2) The resulting voltage is sampled onthe hold capacitor during the signal store. As withDeconvolution mode, the DC output level of the APSPcan be adjusted using the bias Vadj. This method ofperforming the Peak mode operation of the APSP differsfrom previous versions of the chip, but was implementedto ensure that in both Peak and Deconvolution modes thepolarity of the output signal is consistent.Figure 10. Output of APSP in Peak modeFigure 10 shows the output of the APSP (before thehold capacitor) operating in Peak mode. The gain of thefull analogue chain up to this point is 100mV /mip with anon linearity of less than 0.6% over a 5 mip range. Thenon linearity in Peak mode is better than deconvolutionmode because in deconvolution mode the shaper signal issampled on the rising edge which may be prone to slewingeffects for large signals. The power consumption of theAPSP is 0.2mW.6. ANALOGUE MULTIPLEXERThe analogue multiplexer uses the same three levelcurrent mode architecture as with previous versions of thechip – with a few refinements. Firstly, the resistor used toconvert the APSP voltage into a current has been madeprogrammable with a choice of five values. This is to trimthe multiplexer gain since the resistor value is only knownto 20% accuracy. In addition, to overcome problemsfound in previous versions, channels which are notconnected through to the output have their currentsdumped into a load device. This is wasteful of power, butit ensures that channel readout does not affect the voltagesgenerated on nodes within the multiplexer. The analoguegain at the output of the multiplexer is 100µA / mip. Adigital header, which precedes the output of the data fromthe 128 analogue channels, takes the value of  +/- 400µA(HI / LO respectively). With the input bias set to 50µAthe power consumption is  22mW.7. OUTPUT BUFFERFigure 11. Schematic of output buffer.The multiplexer output is converted into a differentialbi-directional current by the circuit shown in figure 11.The output has an analogue gain of +/- 1mA / mip and adigital header of +/- 4mA (HI and LO respectively). Thebuffer has a power consumption of 20mW. Format of thedata produced at the output of  APV25 is shown in figure12.Figure 12. APV25 data format.8. RESULTSFigure 13. Measured APV25 Readout CycleThe APV25 was received back from fabricationimmediately prior to submission of this paper and iscurrently under test. The chip is fully functional and initialresults demonstrate it is working well as shown in figures13 and 14.Figure 14. Measured APV25 Pulse shapes.9. CONCLUSIONSA new analogue pipeline has been designed in a deep sub-micron process. It is based on the APV6 withmodifications which make use of the increased circuitdensity achievable using this process. Radiation toleranceto LHC requirements has been made using special designtechniques, however SEU tolerance will not be achieveduntil the next version. Currently being tested, the APV25is fully functional and radiation tests are imminent.Further information and test results can be found onhttp://www.rl.ac.uk/med/ .10. ACKNOWLEDGEMENTSWe would like to acknowledge technical supportprovided at CERN. Particular thanks are due to SandroMarchioro and Kostas Kloukinas.11. REFERENCES[1] The APV6 Readout Chip for CMS MicrostripDetectors, M.Raymond et al, Proceedings of 3rd workshopon electronics for LHC experiments, CERN/LHCC/97-60,158-162.[2] Performance of a CMOS Mixed Analogue-DigitalCircuit (APVD) for the Silicon Tracker of CMS,F.Anstotz et al, Proceedings of 4th workshop onelectronics for LHC experiments, CERN/LHCC/98-36,180-184.[3] Total Dose and Single Event Effects (SEE) in a 0.25micron CMOS Technology, F.Faccio et al, Proceedings of4th workshop on electronics for LHC experiments,CERN/LHCC/98-36, 105-113.[4] a 128 Channel Analogue Pipeline Chip for MSGCRead-out at LHC, L.L.Jones et al, Proceedings of 4thworkshop on electronics for LHC experiments,CERN/LHCC/98-36, 185-189.

The APV25 deep submicron readont chip for CMS detectors

The APV25 deep submicron readont chip for CMS detectors

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