Van Bakel, N

Van den Brand, J F J

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DESIGN OF A PROTOTYPE FRONTEND AND BIAS GENERATOR FORA NEW READOUT CHIP FOR LHCbNiels van Bakel, Jo van den BrandFree University of Amsterdam / NIKHEFKarl-Tasso Kno¨pfle, Michael Schmelling, Edgar SexauerMax-Planck-Institute for Nuclear Physics, HeidelbergMartin Feuerstack-RaibleUniversity of HeidelbergNeville Harnew, Nigel SmaleUniversity of OxfordAbstractThis paper presents the design and simulation results ofcomponents for a new LHCb readout chip for the siliconvertex detector, the inner tracking system, the pile-up vetotrigger and the RICH. It is planned to use the same readoutchip for these subdetectors. However, different versions ofthe analog input stages might be developed depending onthe choice of the detector type.In section 1, the specification of the new readout chipnamed Beetle with respect to the different subdetector sys-tems is described. Sections 2 and 3 describe the design andthe simulation results of two test chips. The first chip con-tains different types of frontends for the vertex detector andthe second chip bias generators. Section 4 gives a briefoverview on the future plans for the development towardsa readout chip for LHCb.1 Specification of the readout chipThe Beetle readout chip will contain 128 channels. Eachchannel consists of a charge sensitive preamplifier, a pulseshaper, an analog pipeline of a programmable maximum la-tency of 160 stages with an integrated derandomizing bufferof 16 stages and a serial readout for up to 40 MHz read-out speed. In case of using the chip in the binary pipelinemode, the discriminated output of the shaper is stored intothe pipeline and a fast binary multiplexer is used to read outthe chip at a speed of 80 MHz. Readout multiplexing can bedone in several modes: for fastest readout speed of analogdata, four ports can be used at 40 MHz, each multiplexing32 channels. Two ports multiplexing 64 channels runningat 80 MHz can be used for readout of binary data. For ap-plications which do not demand a fast readout, a single portmultiplexing 128 channels can be used and several chipsemail: Edgar.Sexauer@mpi-hd.mpg.deFigure 1: Layout of the BeetleFE-1.0can be connected to build up a readout daisy chain, sharinga single readout line. In addition to the pipelined data paththe combined signals of four neighbouring discriminators,that are located behind the shaper, are routed off the chip.All digital control and data signals are realized as low volt-age differential signals (LVDS). The chip is programmablevia the standard I2C interface and by another serial inter-face, yet to be defined [1].The requirement on the radiation tolerance is driven bythe application of the chip in the silicon vertex detector. Aradiation level of 2 MRad per year is expected for the front-end chips. With an expected usage time of 5 years, thisleads to a total accumulated dose of 10 MRad [4]. In ordersilicon vertex pile-up veto RICH innerdetector trigger trackersampling frequency 40 MHzL0 trigger rate 1 MHzreadout speed max. 900 ns per eventmax. latency 160  25 nsmulti event buffers 16consecutive L0 triggers yesslow control interface I2Cnumber of channels 220,000 400,000 220,000overall readout pitch 50 µm 50 µm 60 µmmax. power consumption 4 mW per channel 4 mW per channel 2 mW per channnelirradiation dose per year 2 MRad 2 MRad few 100 kRad 1 MRaddetector capacitance 10 pF 4 pF / few pFrequired S/N >14 >8 / >20 >10dynamic range [electrons] 110,000 45,000 / 6  106Table 1: Summary of the requirements on the LHCb readout chip. Empty or multiple entries depend on the detector typedecisionto withstand this demanding dose, several measures havebeen taken. A standard 0.25 µm CMOS process has beenchosen, since recent experience of the RD 49 collaborationshows only minimum threshold voltage shift under irradia-tion. Edgeless layout for NMOS transistors has been usedto prevent an increase in leakage current under irradiation.Guardrings have been used in a systematic way to minimizethe rate of single event effects [2]. The concept of usingforced bias currents in the analog stages instead of fixingnode voltages has been applied, as it has been proven to besuccessful for example in [3].A summary of the requirements on the LHCb readoutchip is shown in table 1.2 Design and simulation of theBeetleFE-1.0 frontend chipThe BeetleFE-1.0 chip contains three different sets of a pro-totype input stage, one of which is intended to be used inthe Beetle readout chip for the silicon vertex detector andthe pile-up veto trigger. Each of the three sets consists offour identical channels to allow studies of channel to chan-nel crosstalk. Two of the sets use a PMOS device as inputtransistor, whereas the third set uses an NMOS transistor.All numerical values given below refer to the third set, sinceit is expected to most closely match the requirements. Fig-ure 1 shows a layout view of the chip. The size is 22 mm2.The input pads are located on the left side, the output padson the right side. The remaining pads are used for probingpurposes and for the power supply.Each of the amplifier channels consists of a charge sensi-tive preamplifier, an active CR-RC shaper and a subsequentbuffer. A schematic drawing of this configuration can beseen in Fig. 2. The transistors in the feedback of both stagesbuffercharge sensitive preamplifierpulse shapingstageFigure 2: Principle schematic of the input stage with acharge sensitive preamplifier followed by an active CR-RCpulse shaping stage and a bufferare used as adjustable resistors. The buffer is realized witha standard source follower. The opamp cell of the preampli-fier and the shaper use the well established folded cascodeconfiguration. To a good approximation the noise of thisamplifier circuit is determined by the input transistor of thepreamplifier and its biasing. The power consumption is re-stricted by the silicon vertex detector specification to 4 mWper channel, for which the preamplifier has been optimized.The thermal noise as a function of the input capacitanceCinputcan be calculated byENCthermalCinput= es(1 + )  kT3  Tpeak gmwhere Tpeakis the peaking time, gmthe transconductanceof the input transistor and  the bulk-source transconduc-tance of the input transistor. The 1=f noise can be neglectedin this application, since the band pass characteristic of theshaping stage attenuates the low frequencies. In principle,the designer can choose the shaping time and the gm, whichis defined by the transistor geometry and the bias current.The pulse shape is constrained by the LHC bunch crossingfrequency, since any shaped signal needs to return to zero25 ns after its maximum to avoid a possible pile-up. The ge-ometry can be optimized for minimum noise, since gmrisesproportional to W=L whereas the gate capacitance (whichcontributes to the load capacitance of the amplifying stage)rises with W  L. The value of  rises with decreasing L.However, for this first submission, a set of values has beenpower consumption slope of the noise function0.88 mW 46.5 e /pF1.13 mW 41.4 e /pF1.38 mW 37.5 e /pF1.63 mW 35.5 e /pF1.88 mW 33.6 e /pFTable 2: Slope of the calculated noise function for differentvalues of power consumptionchosen that distribute around the optimum set of values tomake a comparison between the calculated noise values andthe measurements. Table 2 lists calculated values of theslope of the noise function for different bias settings as afunction of the total power consumption for one frontendchannel of the third set. The offset of the noise function isnot calculated, since the final layout of the input protectiondiodes and the input pads, that contribute a considerableamount of the input capacitance, is not yet defined.settings for silicon strip detectorIds        = 270uAC(load) = 10pFpower consumption                 1.2mW25% remainderof peak voltagepeaking time25ns25nstime [s]output [V]Figure 3: Transient response on a delta-shaped signal of11,000 electronsThe pulse shape of the frontend depends on the bias set-tings of the preamplifier as well as on the time constants ofthe shaping stage. Figure 3 shows an example of a simu-lated pulse shape from a signal of 11,000 electrons (whichcorresponds to a minimum ionizing particle in the siliconstrip detector) with optimized settings for the silicon stripdetector. The falling edge of the shaped pulse leads to anacceptable remainder of 25% of the peak voltage at 25 nsafter the peaking time.−10 −8 −6 −4 −2 0 2 4 6 8 10MIP8509009501000105011001150120012501300output voltagePeak Voltage vs. Input Charge1 MIP = 11.000 electronsFigure 4: Peak voltage at the output of the frontend as afunction of the input charge (1 MIP = 11,000 electrons) fora load capacitance of 0 pF (upper curve), 4 pF and 10 pF(lower curve)The frontend has been designed to have a dynamic rangebetween –10 MIP and +10 MIP, as demanded by the speci-fications of the subdetectors. A deviation from linearity of5% is accepted. Figure 4 shows the simulated peak voltageas a function of the input charge for three different valuesof the load capacitance. The gain of the complete fron-tend is simulated to be 20.4 mV/MIP, 19.0 mV/MIP and14.5 mV/MIP for a load capacitance of 0 pF, 4 pF and 10 pF,respectively.peakmaximum at approx. 1/(2   t      )pioutput voltagefrequency~1/f2~fFigure 5: Frequency response of the pulse shaping stageThe frequency response of the pulse shaping stageis plotted in Fig. 5. As expected for a semigaussianpulse shape, the frequency sweep shows a maximum atfmax=1=(2tpeak). This closely resembles the value fortpeak=20 ns obtained from the transient simulation.type of current source maximum load small signal power size(I = 1%) resistance consumption [µm2](1) opamp feedback 1.06 V 4 M 2.35 mW 164 x 61(2) opamp feedback and regular cascode output 1.94 V 14 M 2.5 mW 189 x 61(3) regular cascode 1.93 V 17 M 599 µW 84 x 23Table 3: Specifications for the three different current source options3 Design and simulation of theBeetleBG-1.0 bias generator chipThe bias generator chip BeetleBG-1.0 contains 3 differenttypes of current sources, a voltage digital-to-analog con-verter (DAC), a current DAC and test structures that willbe used to study the change of transistor parameters underirradiation. Figure 6 shows a layout view of the chip. Thesize of the chip is 22 mm2 and the components are laidout in such a way that the chip can be directly bonded tothe BeetleFE chip to allow for frontend biasing and coupledtesting.Figure 6: Layout of the BeetleBG-1.0The three different current sources vary with complex-ity and performance. Table 3 lists the three different typeswith their simulated values. The current source (1) usesan opamp feedback. The second also uses an opamp feed-back system but improves the small signal resistance by us-ing a regular cascode at the output. The third choice usesonly a regular cascode and relies on the fact that the chosenprocess has minimum threshold voltage shift and will notneed compensation for radiation damage. The nominal cur-rent of the opamp feedback with a regular cascode output is300 µA, whereas the others are 100 µA.The voltage DAC uses an R-2R-ladder configuration withΩ = 1% at 70 k∆ Ωinternal resistance = 2.5 kΩ= 5% at 32 k∆offset voltage = 1.2 mVoutput [V]load resistance [10E4 Ohms]Figure 7: Output voltage of the voltage DAC (LSB is setin the upper curve) and offset voltage versus the load resis-tancea resolution of 10 bit and an output range from rail to rail,that is from 0 V to 2.5 V. The 3.0 k resistors are of then+ diffusion type. The power consumption of the DAC is690 µW. Figure 7 shows a plot of the output voltage forthe least significant bit set as a function of the load resis-tance. A change in the output voltage of 1% is simulatedat a load resistance of 70 k. The lower curve in this plotshows the offset voltage, which has an acceptable value of1.2 mV. The differential non-linearity caused by the resis-tance of the switches simulates to be 8 mV. The resolutionof the DAC will be lowered for the final version, the highresolution of this prototype version has been chosen to learnabout mismatch of devices in this technology.I = 1.16uADelta = 1% Delta = 2%leakage current 6.5nAoutput current for 1bitoutput current [A]load voltage [V]Figure 8: Output current of the current DAC (LSB is set)versus load voltage (upper curve) and simulated leakagecurrent (lower curve)The current DAC consists of 1024 conventional PMOStransistors with a W/L ratio of 0.6µm/3µm to optimize thecurrent source to the LSB. Each bit switches on 2n paralleltransistors, acting as a current source. Figure 8 shows thesimulated output current for the LSB set as a function of theload voltage. A change of 2% occurs at a load of 1.5 V. Thelower curve in the plot shows the simulated leakage currentof 6.5 nA, which can be neglected in this application. As forthe voltage DAC, it is foreseen to go to a smaller resolutionin the final version of the current DAC. The study of leakagecurrent and the transistor mismatch will be performed onthis prototype version.The test structures contain minimum size conventionalPMOS and NMOS transistors, PMOS and NMOS transis-tor with an edgeless layout and conventional transistors withthe same effective geometric values as the edgeless transis-tors. In addition, the sizeable NMOS input transistor, usedin the third set on the BeetleFE-1.0, has been added. Thebehaviour on irradiation will be studied on these devicesand compared to results, obtained from other processes.4 Future milestonesIt is intended to submit further components by the end of1999, which include an iteration of the frontend, a calibration pulse generator, a comparator stage, a pipeline capacitor array including a pipeline controllogic a multiplexer with an output buffer.We plan to submit the first version of a complete readoutchip in October 2000. A final version that can be used inthe LHCb experiment, should be submitted by the end of2001. Status reports will be available in [1].References[1] M. Feuerstack-Raible, Beetle - A Readout Chip forLHCb, http://wwwasic.ihep.uni-heidelberg.de/lhcb/[2] F. Faccio et al., Total Dose and Single EventEffects (SEE) in a 0.25µm CMOS Technology,CERN/LHCC/98-36[3] W. Fallot-Burghardt, A CMOS Mixed-Signal ReadoutChip for the Microstrip Detectors of HERA-B, Ph.D.Thesis, Heidelberg 1998[4] T. Ruf, Vertex Front-End Electronics,http://lhcb.cern.ch/vertexdetector/html/fee.htm

Design of a prototype frontend and bias generator for a new readout chip for LHCb

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