Hasuko, K

Homma, K

Ikeno, M

Iwasaki, H

Kobayashi, T

Ohska, T K

Saitó, M

Sasaki, O

Yoshida, M

CERN Document Server

ASD for the Thin Gap Chambers in the LHC Atlas ExperimentO. Sasaki1, M. Yoshida2, K. Hasuko2, K. Homma2, M. Ikeno1,H. Iwasaki1, T. Kobayashi2, T.K. Ohska1, M. Saito1 and K. Sato21High Energy Accelerator Research Organization (KEK)Institute of Particle and Nuclear Studies (IPNS)1-1 Oho Tsukuba Ibaraki, 305-0801 JAPAN2International Center for Elementary Particle Physics (ICEPP), University of Tokyo7-3-1 Hongo, Bunkyo-ku, Tokyo, 113-0033 JAPANAbstractAn amplifier-shaper-discriminator (ASD) IC and 16-ch ASDboard were designed and built for Thin Gap Chambers in theforward muon trigger system of the LHC Atlas experiment.The ASD IC uses SONY Analog Master Slice bipolartechnology. The IC contains 4 channels in a QFP48 package.The gain  of its first stage (preamplifier) is approximately0.8V/pC and the output from the preamplifier is received bya shaper (main-amplifier) with a gain of 7. The baselinerestoration circuit is incorporated in the main-amplifier. Thethreshold voltage for discriminator section is common to the4 channels and their digital output level is LVDS-compatible.The IC also has an analog output of the preamplifier. Theequivalent noise charge at input capacitance of 150 pF isaround 7500 electrons. The power dissipation with LDVSoutputs (100 Ω load) is 59 mW/ch. Beam tests of the ASDboards were made and showed good performance. The resultsof the irradiation tests by gamma ray and neutrons provedthat the circuits retains the properties required for the TGCreadout after 10 years of LHC running.I.  INTRODUCTIONThe Atlas experiment in the LHC uses Thin GapChambers (TGC) [1,2] as its forward muon trigger detectors[3,4]. The total number of TGCs are 3600 and we will bedealing with TGC signals from their anodes (several wiresare ganged together) and strips, totaling nearly 330kchannels. The capacitance of  the TGC as a signal source is afew hundred pF, which comes from  the thin gap structure ofthe chamber and is rather large capacitance when comparedwith that of an ordinary chamber. The requirement of fastsignal processing and the characteristic of large detectorcapacitance contradict each other when we design a low-noise preamplifier. Much attention was paid to the processchoice and circuit design for the TGC application. The ASDas TGC front-end electronics must have a good timeresolution for bunch-crossing identification and a high ratecapability to cope with high background rate (100 kHz/channel) and must be robust for the longtime operationwithout maintenance.II.  CIRCUIT DESIGNBecause the signal source has relatively large capacitanceand because fast signal shaping as well as low noise are therequirements on the amplifiers, transistors with large gm arepreferred. Hence we chose to base the amplifiers on bipolartransistors [5,6]. The chip has been developed incollaboration with SONY Corporation, using their bipolar‘Analog Master Slice Process’. This semi-custom processprovides prefabricated NPN and PNP transistors, resistorsand capacitors, so that a designer has to design using theseelements that are predetermined beforehand for the siliconwafer. The base-structure we used contains 850 NPNtransistors, 3834 PNP transistors, 1738 resistors and 42capacitors, totaling approximately 1000 usable elements.There are five kinds of NPN transistors on the chip includinglow noise transistors and power transistors. The standardtransistor has fT = 3.2 GHz. The low noise transistor has fT =950 MHz and base-spread resistance rbb’ = 17.5 Ω.Availability of the low-noise transistors with very low rbb’was one of the motivation to use the process. There also aretwo kinds of PNP transistors of which the standard one has fT= 300 MHz. Capacitors are of 2 pF and 20 pF value totaling408 pF (Metal Insulator Semiconductor, MIS capacitor) intotal. resistors are of either 8 kΩ or 2.5 kΩ (poly-silicon),297 Ω (diffused) and 129 Ω (diffused). Figure 1 : Block diagram of the ASD chip.offsetsettingcomparatorVthNON-INVINVCbi2 iA BSWCf = 1 pFRf= 16 kΩG ≈ 7preamplifierRfCfFigure 2 : Preamplifier, baseline restorer and main-amplifierschematics.Figure3 : Comparator circuit schematics.Table 1 : TGC ASD chip characteristicsProcess SONY Analog Master Slicebipolar semi-customSpecification preamplifier with a gain of 0.8 V/pC16 nsec integration timeinput impedance of around 80 Ωopen-emitter analog outputmain-amplifier with a gain of 7baseline restoration circuitscomparator with LVDS outputsENC ~ 7500 electrons at Cb = 150 pF4 channels in a QFP48 plastic packagethreshold voltage common for all 4 channelsrequired voltage : +/- 3V, GND59 mW/ch when driving a 100 Ω load(46 mW in ASD chip and 13 mW at LDVSreceiver end)Figure 4: PSPICE simulations of the preamplifier, main-amplifierand comparator outputs.A block diagram of the ASD chip is shown in Figure 1,with schematics in Figure 2 and 3. Its first stage is acommon-emitter cascade charge amplifier. The input stage ofthe preamplifier is implemented with the low-noise NPNtransistor with rbb’ of 17.5 Ω. The relatively large capacitance(higher than 10 pF between the collector and substrate) of thetransistor disfavors the use of the transistor in common-baseconfiguration which is usually employed in preamplifiers forchambers [7]. The collector current of the head transistor isset high (0.9 mA)  to achieve large gm, which have advantageto achieve lower noise at large detector capacitance. Theintegration constant is set to 16 ns. The gain of thepreamplifier stage is approximately 0.8 V/pC. An emitterfollower output of this preamplifier stage is provided formonitoring.The second stage consists of a main-amplifier with abaseline restorer and differential outputs. The main-amplifiersection has a gain of 7. Depending upon the outputdifferential signal level seen by the switch control section,the switch connects to the “A” side or to the “B” side ofFigure 1. When the switch is connected to the “A” side, thecapacitor Cb will be charged from the current source by theamount of ‘i’. When the switch is connected to the ‘B’ side,-0.5 ~ -0.1pC impulse inputs02004000 20 40 60 80 100 120 140Time    (ns)preamplifier outputs (mV)0500100015000 20 40 60 80 100 120 140Time    (ns)mainamplifier outputs (mV)1000120014000 20 40 60 80 100 120 140Time    (ns)comparator outputs (mV)comparator outputs (mV)mainamplifier outputs (mV)the capacitor will be discharged by the amount ‘i’, resultingin stabilized DC output levels, or a baseline restoration. Inother words, the circuit makes the baseline level of thedifferential outputs from the main-amplifier to be equal.Following the main-amplifier is an offset setting whichtransforms the main-amplifier outputs to the levels requiredat the inputs to the comparator, where offset voltage iscontrolled by DC voltage (Vth) supplied from outside of thechip. The comparator is shown in Figure 3. Its outputsconform to the Low Voltage Differential Signalling standard,LVDS, to assure drivability and immunity against noise andminimizing power.By design, this circuit can be used for both wire and stripsignals by setting an appropriate threshold level. Table 1 is asummary of this chip’s characteristics.Figure 4 shows the result of a PSPICE simulation of thepreamplifier output, the main-amplifier differential outputsand the comparator LVDS outputs against impulse inputs of -0.1 ~ -0.5 pC charge. Dynamic range (non-saturated range)of the preamplifier is negative / positive impulse charge inputof from -1.2 to +2.0 pC. The slewing rate of the preamplifieralso limits the linearity for large positive charge inputs. Thedynamic range and the gain of the preamplifier observed atthe buffered direct output depends on the external load and isless than the internal one. The circuit can successfully acceptsignals of 5 MHz or higher frequency.4 channels of ASDs was fabricated on a 3.1mm X 3.1mmdie. The threshold voltage is common to 4 channels. In thelayout work of the IC, we paid much attention to reduceinterference between analog and digital signals and cross-talkamong channels. Both ground and power patterns and I/Opads for the analog part are separated from those for thedigital part. The chip is housed in a QFP48 package. For theprotection from static charge, diodes are attached between allI/O pads and the most positive / negative voltage exceptingthose for ground and DC powers.Figure 5 : Analog and digital signals from the ASD for impulseinputs from –0.1 to –0.5 pC.Figure 6 : Overall time walk of the ASD outputs due to the inputcharge variation.Figure 7 : Measured the ENC (closed circle) and calculated ENC(open circle) using design parameters of the preamplifier andmeasured impulse response of the evaluation system.III.  PERFORMANCEThe analog and digital signals from the ASD chip forimpulse inputs from -0.1 to -0.5 pC are shown in Figure 5.The overall time walk of the comparator outputs due to theinput charge variation of between -0.1 pC to -2 pC is lessthan 2 ns, when the threshold is set at 0.01 pC equivalent, asshown in Figure 6.We also tested the performance of the main-amplifier andcomparator using prototype chips where the preamplifier, themain-amplifier and the comparator were fabricatedseparately for independent study. In order to checkcomparator characteristics, we measured propagation delay0246810120 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2Impulse Input Charge (pC)Propagation Delay (nsec)02000400060008000100000 50 100 150 200 250 300Input Capacitance (pF)Equivalent Noize Charge (e)while changing conditions such as: varying over-the-threshold-voltage of the input pulse that has fixed rise time /varying over-the-threshold-voltage of the input pulse that hasfixed slope / varying rise time while input pulse height waskept constant. The result show that the time walk of thecomparator was within less than 2 ns under these conditions.These results agree with predictions by the PSPICE.Temperature dependence of the preamplifier gain wasapproximately -0.08 %/oC. The feedback capacitor of thepreamplifier is supposed to be the major contributor totemperature dependence. The ENC was measured as afunction of the input capacitance as shown in Figure 7. Wecalculated the ENC using design parameters of thepreamplifier and measured impulse response of theevaluation system. The calculation reproduces the measureddata with the rbb’ of 15 Ω and the hfe of 90. Cross-talk amongchannels were less than 0.5 % when analog output pins areleft open. If the open-emitter buffer for the analog outputdrives 50 Ω load, the cross-talk became 3 times larger.Influence of the digital part on the analog part was much lessthan the cross-talk between channels.IV.  ASD BOARDThe 16-ch ASD board was designed for wire signals andstrip signals from the TGC. Each board contains 4 ASD ICswith protection circuits and a test pulse circuit that receives atest pulse and distributes a charge impulse to each channel.The board design is common for all TGC chambers. LVDSlogic signals from the ASD board are transmitted through a20-pair twisted-pair cable and a preamplifier output througha LEMO type connector. DC power, ground, thresholdvoltage (common over a channel) and test pulse are suppliedback to the ASD board via the same twisted-pair cable. Inorder to reduce the production cost, the board was designedas a 2-layer PCB. Devices are surface mounted except forconnectors on only one side.V.  BEAM TESTWe tested TGCs with the ASD ICs at KEK and CERN in1998. We used pion beams with essentially no backgroundhits at KEK. Whereas at CERN the chamber was tested usingmuon beams under gamma irradiation. The time jitters andthe efficiencies were measured varying the high voltage tothe TGC and the gamma irradiation rate. The thresholdvoltage was set at 5 times of the ENC of the ASD. The timejitters measured are consistent with the ones using hybridASD circuits tested before. The rate dependence of theefficiency at applied voltage of 3.0kV is shown in Figure 8.The efficiency is high enough even at five times thepredicted background rate (150 Hz/cm2) at the inner station(the worst place). The ASD boards together with the Module-0 TGC chambers perform as expected in the real ATLASenvironment. During the beam tests, we could operate theASD boards very stably and enough performance wasproved.Figure 8 : Efficiency versus background rate for the wire signal.Figure 9 : Gain changes of the ASD chips versus gamma dose.VI.  IRRADIATION TESTAccording to the simulation of the expected radiationenvironment in ATLAS [8], radiation levels at the TGCwheels are an ionization dose of 0.62 Gy/yr and 1.0 x 10101MeV equivalent neutron/cm2/yr. Taking into account theuncertainty in the estimation, a safety factor of four isrequired [8]. The bipolar transistors, which have a highersensitivity to radiation damage, require an additional factorof 1.5 for the neutron flux and a factor of five for theionizing dose. The radiation tolerance criteria at the worstlocation of the TGC trigger station for 10 years running is anionization dose of 130 Gy and 1.2 x 1012 1MeV equivalentneutrons/cm2.808590951001051101 10 10 2 10 3Rate (Hz/cm2)Efficiency (%)025050075010001250150017502000225025001 10 10 2 10 3 10 4 10 5gamma dose(Gy)gain (mV/pC)Figure 10 : Normalized hFE values as a function of IC for NPNtransistors for various neutron fluences.Figure 11 : Gain of the ASD chips versus neutron fluence.The gamma irradiation tests were performed using 60Coand 137Cs gamma ray sources at the rates of 6.7 kGy/hour and5 Gy/hour. The hFE parameters of the transistors, and the gainand the ENC of the ASD ICs were measured. The resultshowed that the degradation in hFE at the dose of 100 Gy iswithin 10%. The gain change of the preamplifier part of theASD chip were measured up to the total dose of 30 kGy, asshown in Figure 9. Changes in both the gain and the ENCafter 100 Gy irradiation are within the range of the piece-to-piece variation.The neutron irradiation tests were performed using 12GeVProton Synchrotron at KEK and the Prospero facility inFrance. Figure 10 shows the hFE values normalized to theones before the irradiation as a function of IC. After theirradiation of 1.1x1012 1MeV equivalent neutrons/cm2, thedecrease of the hFE at the nominal value of IC was found to beless than 10%. Figure 11 shows the gain difference after theirradiation of 1.2x1012 1MeV equivalent neutrons/cm2 iswithin 5%. There was no apparent difference in the ENC upto 1.7x1013 1MeV equivalent neutrons/cm2.It was proved that the ASD chips and the components ofthe ASD board retain the properties required for the TGCreadout after 10 years of LHC running even at the location ofthe worst background condition.V. SUMMARYWe have designed and built a chip containing 4 channelsof  ASDs for the TGCs of the Atlas LHC experiment usingSONY semi-custom Analog Master Slice bipolar process. Wealso developed 16-channel ASD boards and performed beamtests with real TGCs at both KEK and CERN. Irradiation testusing gamma ray and neutrons were performed and thenradiation tolerance of the chip has been assured. The mass-production (100k pieces) of the chips has been done insummer of 1999 and the assembling of the ASD boards (23k)is scheduled in the first quarter of 2000.VIII.  REFERENCES[1] G.Mikenberg, "Thin-gap gas chambers for hadroniccalorimetry", Nucl. Instr. Methods, vol. A265, pp. 223-227, 1988.[2] Y.Arai et al., "Timing optimization of thin gap chambersfor the use in the ATLAS muon end-cap trigger", Nucl.Instr. Methods, vol. A367, pp. 398-401, 1995.[3] ATLAS Muon Technical Design Report,CERN/LHCC/97-22 ATLAS TDR 10, May 1997.[4] ATLAS First-Level Trigger Technical Design Report,CERN/LHCC/98-14 ATLAS TDR 14, June. 1998.[5] P.D’Angelo et al., "Analysis of low noise transistor headamplifiers for high energy applications of silicondetectors", Nucl. Instr. Methods, vol. 193, pp. 533-538,1982.[6] Veljko Radeka, "Low-noise Techniques in Detectors",Ann. Rev. Part. Sci.,  vol. 38, pp. 217-277, 1988.[7] M.M.Morii et al., "Low-noise fast bipolar transistors fordetector preamplifiers", IEEE Transactions on NuclearScience, vol. NS-36, pp. 407-411, 1987.[8] “ATLAS policy on radiation tolerant electronics”,http://www.cern.ch/Atlas/GROUPS/FRONTEND/WWW/radtol2.ps.00.20.40.60.811.210 -6 10 -5 10 -4 10 -3 10 -2IC(A)h FE/hFE0025050075010001250150017502000225025000 500 1000 1500 2000x 10101 MeV neutron fluence(n/cm2)gain (mV/pC)

ASD for the thin gap chambers in the LHC ATLAS experiment

ASD for the thin gap chambers in the LHC ATLAS experiment

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