Kaplon, J

Lacasta, C

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WAFER SCREENING OF THE FRONT−END ASICS FOR ATLAS SCTCarlos Lacasta, Instituto de Física Corpuscular, Valencia, Spain (e−mail: Lacasta@ific.uv.es)Jan Kaplon, CERN, Geneva, Switzerland (e−mail: Jan.Kaplon@cern.ch) AbstractThe continuous increase in volume of silicon trackersin the coming experiments poses a number of new issuesto unravel. Among them, the high number of detectorreadout modules to be built in a relatively quick timewill require the use of preselected ASICs. In theparticular case of the ATLAS SCT, where about 6million channels have to be read out with little chancefor replacement of the electronics, that becomes aconsiderable challenge. Specific architecture features ofthe front−end chips will call for very specific anddedicated electronic testers to provide a full and efficientcharacterization. This paper describes the system builtfor the preselection and characterization of the ABCDfront−end chip to be used in the readout of the ATLASSCT microstrip silicon sensors. The system has beenused successfully during the last year to tag the 6000ABCD chips that have been built up to now and has beenupgraded to cope with the new features of the lastversion of the chip.1.  THE ABCD CHIP.The Atlas Binary Chip DMILL (ABCD [3]) design isa single chip implementation of the binary readoutarchitecture for silicon strip detectors in the ATLASSemiconductor Tracker [1]. The Radiation Hard DMILLtechnology [2], in which the ABCD chip is fabricated,offers the unique possibility of combining a bipolarfront−end amplifier/comparator with the CMOS logic ina single chip.A major issue in the binary architecture implementedin the ABCD chip is the matching between the channels.Two versions of the chip, presenting different solutionsof this problem, are currently under development. TheABCD2T version has a gain of 80 mV/fC and a 4−bitDAC for the threshold correction implemented in eachchannel, together with a common threshold, controlledby a 8−bit DAC, for all the channels, allowing to tunethe matching between them. The second version, theABCD2NT chip, with only the common threshold for its128 channels, has twice higher gain before thecomparator and a layout optimized for better matching. The block diagram of the chip is shown in Fig. 1. Thepreamplifier−shaper circuit provides signals with apeaking time of 25 ns, sufficient to keep the time walkof the discriminator in the range of 12 ns and a doublepeak resolution of 50 ns. This circuit is followed by acomparator whose threshold is applied channel bychannel as explained above. The binary data from thediscriminator are latched in the input register in eitherlevel or edge sensing mode −with a time resolution of25 ns− and clocked into a 132−cell deep pipeline. Foreach trigger, the data are transferred from the pipeline tothe second level buffer, 128 bits wide and 24 locationsdeep, that serves as a derandomizing buffer whichremoves the fluctuations from the L1 trigger distribution.It will store three bits of data per channel, correspondingto the three beam crossings centered on the L1 triggertime, and are set if the input was above threshold duringthe corresponding crossings. The data compression logicwill take these data and suppress the empty channelsmaking the chip output only the hits which match thepattern programmed in the configuration register. Thereadout logic will be responsible for the capture andrelease of the token and outputting data from the chip.The readout circuit always waits until the token arrivesand on its arrival it outputs the data of the chip. If thechip is in the middle of the chain, sends a token to thenext chip. If the chip is configured in send−id mode, itwill output the contents of the configuration registerinstead of the data from the channels.Fig. 1. Block diagram of the ABCD chip.In addition to the basic functional blocks describedabove, the ABCD comprises a calibration circuitry forinternal generation of calibration pulses whoseamplitude is set by a 8−bit DAC and their delay relativeto the clock phase is controlled by a delay buffer of 6−bit resolution. 2.  THE SETUPThe setup, as sketched in Fig. 2, is based on a KarlSUSS PA200−II probe station with a fully motorizedchuck stage whose movement is controlled through theGPIB interface. The functions implemented in theABCD chip for internal testability, like internalcalibration circuitry or pulsing input register function,allowed to build a simple and robust system where allthe communication to the chip is done via digital serialinterface. Since the goal is to test the chip with a highfrequency clock −up to 50 Mhz−, all signals delivered toand received from the chip had to be buffered on thePCB close to the needles. To this end, a custom designedprobe card (PCB) has been made with standardtechnology and 64 needles with the standard pitch of200 µmFig. 2. Schematic diagram of the wafer test system.The chip control and data acquisition is based on twoVME modules: a sequencer (SEQSI [4]) which providesthe clock and control signals to the chip, and a datareceiver and decoder (DRAFT [5]).For measurements of the characteristics of the digital−to−analogue converters on the chip, a HP voltmeter withan analogue multiplexer is used, and it is connected tothe system through the GPIB bus. The same device isused to control the vacuum to fix the wafer onto theprober chuck. A Tektronics power supply is used toprovide the chip with the digital and analogue bias andalso to measure the power consumption of those lines.All the system is controlled by a dedicated programwritten in C++ and running in a PC under Windows 95.The program controls the VME and the GPIB buses. Itprograms the sequencer to set the phase between theclock and the command line of the chip, builds thecommands to carry out the tests and reads out theDRAFT. On the GPIB side, it controls all themovements of the wafer prober, sets up the voltmetersand power supplies and reads from them all the data.Probe movements are programmed very cautiously andall the system stops whenever any disagreement is foundbetween programmed and monitored coordinates or thevacuum fails. Concerning the tests, it allows toindependently select and configure any of them to bedone and also takes care of the data acquisition andstorage using standard packages to compress the data inorder to save as much space as possible. In total, thesystem takes between 300 and 200 seconds to performthe complete set of tests in a chip, depending on whetherthe chip is a trim dac version or not. On a second stage, the data collected by theacquisition program is analyzed using a separatesoftware in order to effectively classify the chips. It alsoproduces a sort of data summary file and provides theinformation needed to feed a chip database to help in thecontrol of chip quality and distribution.3.  TEST PROCEDURE.The ABCD chips will be assembled on the hybrids asunpacked devices and, in consequence, the chippreselection and characterization process has to becarried out at the level of wafer screening. Thecharacterization process needs to be complete, accurateand as fast as possible since about 50000 chips need tobe preselected. Inasmuch as the ABCD chip follows thebinary architecture, a considerable amount ofmeasurements are needed to obtain any information onthe analogue performance of the front−end. Also acomplete set of digital tests proving the readout protocol,different modes of operation and functionality of thewhole logic, together with the characterization of theon−chip digital to analogue converters (DAC), need tobe designed and carried out.3.1. Digital tests.A number of tests are made to check all the digitalfunctionalities of the chip. The main characteristics toperuse are related to chip control, inter−chipcommunication and data compression. Additionally,some functionalities like channel masking andredundancy mechanisms should be proven. All the testsmake an extensive use of some of the testing toolsprovided by the chip, like pulsing the input register orgenerating output patterns through the mask register. Toevaluate the performance of the chip in the differenttests, four different patterns with a length of 128 bits areusually injected:• a sequence of 128 ones,• a sequence of 010101...01,• a sequence of 101010...10 and• a sequence with 30% of the channels set toone randomly.In order to evaluate the performance of the chip underthe different tests, a fixed number of events weretriggered for each of the patterns and the resultingefficiency studied.Another key issue concerning the performance of thedigital part is to determine the maximum speed of theselected chips. Since the maximum frequency clockattainable in the setup −50 Mhz− is lower than themaximum speed of the ABCD chip for nominal biasconditions1, the chip performance degradation was1Results from IMS tester performed on diced chips showfunctionality up to 70 Mhz.simulated by lowering the power supply. For that reason,all the tests were repeated for two different clockfrequencies −nominal 40 MHz and 50 Mhz− and forseveral values of the digital power supply (Vdd): from3.3 V up to 4.2 V. The minimum Vdd for which a chipstill shows full efficiency at 50 MHz was used to classifythem according to their speed performance and in theyield calculation. This is shown in Fig. 3. The histogramhas as X−Y coordinates the cells in the wafer and on theZ axis how far from the nominal Vdd −4 V− the chipstill shows full functionality at 50 MHz. The next paragraphs describe the digital testsperformed:• Configuration register input/output:This is one of the most determinant tests because itproves that the chip can be configured. Theconfiguration register is written with random values,keeping the chip always as master and end chip. Thevalues are then compared with the data returned bythe chip in the send identification mode. Sinceaddressing is not meant to be test here, the universaladdress is used. • Addressing:The ABCD is supposed to be mounted in a modulepopulated with 12 chips. In order to configure eachof the ABCDs independently an addressingmechanism has been implemented which is testedhere. The chip is given a random address and it isconfigured using that address. The value is comparedwith the one returned in the chip data.An extra test is done at this level: The L1 counter isfollowed and its value stored. It should start at 0 andincrease in steps of 1.• Input Register:To check the functionality of the mask register, thefour patterns are loaded in the mask register and theinput register is pulsed. Pulsing the input register setsto one the 128 channels. At the output, only thechannels allowed in the mask register should be atone.• Input Lines:The functionality of both input lines for the chipclock and commands is tested by injecting the fourpatterns through the mask register and sending theclock and the commands through both lines. Theoutput is contrasted with the patterns.• Fake slave:The chip is set as master and middle chip. In the firstpart of the test the token transmission through bothlines is checked. In a second stage, a sequencesimulating the data of a slave chip is injected throughboth input lines of the chip and contrasted with itsoutput. The chip is also provided with a patternprogramed in the mask register in order to check thatit merges properly its data with that of the slave.• Slave:The chip is set as slave and end chip. The fourpatterns are injected through the mask register andthe token sent, after each trigger, through both inputlines. The chip output is also searched on those lines.Cell number0 12 34 56 78Cell number024681012141618204-Vddmin (V)-0.4-0.200.20.40.6Minimum Vdd  100% eff.Fig. 3. Wafer map of the maximum distance in voltsdown the nominal Vdd −4 V− at which the chips,operated at 50 Mhz, still show full digital functionality.The X−Y plane represents the cells in the wafer. 3.2 Power Consumption.The setup measures the power consumption both ofthe digital part and the analogue part. To simulate thenominal requirements for the ATLAS SCT occupancyand L1 trigger rate, the measurement was done applyinga 100 kHz trigger with an occupancy of 3% of thechannels selected randomly. Fig. 5 shows the averagevalues obtained for all the chips passing the digital testsin one of the wafers. Although the distributions are quitenarrow, still some chips are far away from the peak.Those chips, with such a high power consumption, arerejected during the selection process due to possibleweaknesses of some parts of the digital logic.DC input current (A)0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10102030405060Slave : 33(1) mAMaster: 49(2) mAWafer19.0 - Digital CurrentDC input currents (A)0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.101020304050607080Slave : 63(1) mAMaster: 63(1) mAWafer19.0 - Analog CurrentFig. 4. Current measured for the digital (upper plot)and analog (lower plot) voltages of the chip.3.3 Digital to Analogue Converters.The ABCD has 3 main DACs whose performancehave to be carefully tested:• Threshold DAC (8 bits),• input transistor current DAC (5 bit) and• shaper current DAC (5 bit)The chip incorporates one additional 8 bit DAC forthe calibration pulse height which is not directly testedand its failure will translate in a deficient analogueperformance. The trim dac version of the chipincorporates an additional DAC per channel toindividually trim the value of the threshold. The testperformed on this DAC are described in 3.4.1.In order to prove the behavior of the three DACs, afull scan on the DAC bits is done and the DC levelsprovided by the chip in its test pads are read with the HPvoltmeter. This will allow to measure their linearity, asshown in Fig. 5, where the relative deviation fromlinearity with respect to the DAC range is also depicted.3.4 Analogue performance.The goal of these tests is to determine the basicanalogue parameters of the front−end: gain, noise anddiscriminator offset spread. To this end, a threshold scanfor three different input charges is done for each channelin every chip, as described in [6]. The input transistorcurrent and the shaper bias are set to the nominal valuesand the chip is driven by a 40 Mhz clock. Three s−curves per channel are fitted to a complementary errorfunction. From the 50% points the gain curve is built andfitted to a straight line. The gain and the offset are takenas the slope and the offset, respectively, of the linear fit.The electronic noise information is also obtained, foreach pulse, from the s−curve fit.Fig. 6 shows the distributions of the gain and noise ofall the no trim dac chips in a wafer.  Gain (mV)0 50 100 150 200 2500246810121416182022Nent = 84     Mean  = 117.622RMS   = 17.9598Chi2 / ndf = 15.1034 / 7Constant = 22.878 +- 0.664164 Mean     = 120.227 +- 0.160052 Sigma    = 6.98516 +- 0.11824 Wafer19.1 - Chip GainNoise (mV)0 5 10 15 20 25 30 35 40 45 5005001000150020002500Nent = 10752  Mean  = 14.4875RMS   = 2.80721Wafer19.1 - NoiseFig. 6. Average chip gain and noise of all the chips in awafer. 3.4.1 Trim DAC test.For the trim dac version of the chip a full scan of thedac bits is done for all the channels and for a fixedcalibration pulse. Applying the same analysis describedfor the gain and offset measurements an overallcharacteristic of the trim DAC is obtained.4. YIELD CALCULATION.To calculate the yield, a selection criteria has beendefined based on the results on the digital and analoguetests, together with the power consumption measurementand the DAC studies. Results from the analogue tests arecorrelated with the digital tests done at different clockfrequencies and Vdd. At any of those points a chip willbe considered as non−functional whenever a singlefailure is found in any digital test, the powerconsumption both in the analogue and the digital partsexceeds 20% the mean value from the wafer, the DACnon linearity is out of range or it has one or more deadchannels. A channel is said to be dead when it does notrespond to the calibration pulse −or its efficiency issmaller than 95%−, its gain is 20% lower than the meanvalue of the wafer or the noise is higher than1500 e − ENC. Programmed (mV)0 100 200 300 400 500 600Meassured (mV)0100200300400500600700Non linearity (×10-3 )-5-4-3-2-1012345Threshold DACProgrammed (µA)0 50 100 150 200 250Meassured (µA)050100150200250300350Non linearity (×10-3 )-15-10-5051015Input transistor current DACProgrammed (µA)0 5 10 15 20 25 30 35Meassured (µA)0510152025303540Non linearity (×10-3 )-15-10-5051015Shaper current DACFig. 5. Linearity of the threshold and bias DACs. The round bullets show how the DC levels change while increasingthe values of the DAC registers. The linear fit performed to the data is also shown. The small squared bullets showthe  deviation from linearity relative to the range of the DAC. Its scale is shown on the right axis.Concerning the DAC linearity, although there is nostrong constrain from the specifications, a selectioncriteria has been defined so that chips will be rejectedwhenever the spread of the non linearity distributionexceeds 1% in the threshold DAC and 10% in the biasDACs.Vdd (V)3.2 3.4 3.6 3.8 4 4.2 4.4Yield00.10.20.30.40.50.60.70.80.9Digital at 50MHzDigital at 40MHz≤2 dead≤1 deadno deadNumber of analysed chips = 127Wafer 19 - TrimFig. 7. The lines labeled as Digital show the yield ofthe digital part of the chip obtained under different testconditions. The line labeled as no dead, shows the finalyield after applying the criteria of the analogue tests,power consumption and DAC linearity. Also the yieldvalues obtained when relaxing the requirement on thenumber of dead channels allowed in the chip areshown.Fig. 7 shows the digital yield for different digitalbiases and clock frequencies. The final value of the yieldafter applying the restrictions on the analogueperformance, power consumption and DACs tests is alsoshown. Typical values of about 30% have been obtainedfrom the wafers of the last process if no dead channels isallowed in any of the chips.As for the analogue performance, a quality factor isdefined as the ratio between the gain and the matching,defined as the spread of the 50% points. This factor isnot directly used in the yield calculation although it iswidely used during the selection of the chips. Thedistribution of the quality factor is shown in Fig. 8 forboth versions of the chip. For the trim dac version, thequality factor is computed without trimming thechannels. On diced chips, and after trimming, a qualityfactor of 20 has also been obtained.  Quality Factor (fC-1)0 5 10 15 20 25 30 35 4005101520253035No trim DACTrim DACQuality FactorFig. 8. Quality factor distribution for all the chips in awafer.5. CONCLUDING REMARKSA system has been built which is able to test all thefunctionalities of the ABCD chip on the wafer. It hasproven to perform fast and accurately, providing all theinformation needed to tag the chips and build a generaldatabase for control and distribution of the chips. Thesystem has been successfully used to test all the ABCDwafers supplied up to now and has been upgraded tocope with the new features of the last versions of thechip.  REFERENCES[1] ATLAS TDR 5, Inner Detector Technical DesignReport, Vol. II, CERN/LHCC/97−17, 30 April1997.[2] RD29 Status Report "DMILL, A Mixed Analog−Digital Radiation hard Technology for High EnergyPhysics Electronics", CERN/LHCC/97−15, 11 Mar.1997.[3] ABCD Chip Specification. Version 2.0, Dec. 12,1998.[4]  SEQSI (RAL PC2935), M. Morrisey.[5]  DRAFT (RAL PC3080), M. Morrissey.[6]  Test on ABCD Chips. ATL−INDET−98−217.

Wafer screening of the front-end ASICs for ATLAS SCT

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