Bevensee, B E

Dressnandt, N

Lam, N

Newcomer, F M

Van Berg, R

Williams, H H

CERN Document Server

Progress in development of the ASDBLR ASIC for the ATLAS TRTB. Bevensee, N. Dressnandt, N. Lam, F.M. Newcomer, R. Van Berg and H.H. WilliamsPhysics Dept., University of Pennsylvania, Philadelphia, Pa. 19104AbstractThe ATLAS TRT straw tracker will consist of morethan 420K straw tubes lled with a Xenon based fastgas located in a magnetic eld of 2T. Some tubes willoperate at rates up to 15 MHz. Stringent signal processinggoals include: the ability to detect energetic TransitionRadiation photons as well as the earliest clustersfrom ionizing tracks without baseline shifts have beendetermined using both simulation tools and measurementstandards set by hand tuned discrete componentprototypes. High channel count and restrictions on cableplant led to the development of custom ASICS to housethe detector mounted front end electronics and digitizedreadout. The ASDBLR is a custom analog bipolar ASICthat provides the full signal processing chain from strawinput to the output logic pulse.A. IntroductionThe straw-tube Transition Radiation Tracker (TRT)in the ATLAS detector at LHC [1] is being designed tooperate at extremely high radiation levels. Some elementsof the 425,000 straw tube detector are expected to operateat rates approaching 20MHz. Each straw has a cathodediameter of 4mm, anode wire diameter of 30m and willbe lled with a gas mixture of 70%Xe+20%CF4+10%C02and operated at a gain of  2 104. Xenon gas improvesthe eciency for stopping TR photons, but lengthensthe ion tail of the current pulse signicantly comparedto more conventional Argon based mixtures. In order toachieve the required 150m track resolution, at high rates,the baseline will need to be stable so that the avalanchesignal from the rst primary electrons can be accuratelydetected. Ionizing tracks will deposit an average of 2KeVresulting in a charge of approximately 20fC at the inputto the amplier during the 7.5ns peaking time. Due tothe circular cathode geometry and the relatively lowvelocity of the primary ions there is signicant variationin the signal shape and total charge. For high eciencyit is necessary to operate at thresholds of 2fC or 200eVequivalent energy loss. Signals of 20-50 times thresholdwill occur frequently making it important that the signalat the input to the comparator be adjusted to reliablyreturn to baseline as soon as possible after the last ofthe drift electrons from a track have arrived at the wire.Radiation and breakdown issues place relatively strictrequirements on the gas gain, making it necessary toemploy low noise design techniques. Finally, the largenumber of detector mounted electronics channels make itimportant to keep the power dissipation as low as feasible.B. ASDBLR ASIC BLOCKSThe eight channel ASDBLR wire chamber ASIC,currently in its third generation, has been developed tomeet the tracking and particle identication objectivesof the ATLAS TRT using inherently radiation tolerantanalog bipolar processes.A block diagram of the rst version of the circuit isshown in Figure 1. A more detailed description of eachFigure 1: Blocks of the ASDBLR Circuitblock may be found in reference [2]. Good common moderejection, both on and o chip is achieved by providingpackage leads to both 150MHz preampliers on eachchannel. All remaining stages are fully dierential. Theshaper provides ion tail cancellation for either Xenon orArgon based gas selected by an externally controlled logiclevel. Ion tail cancellation is designed to operate linearlyover a 600fC range with a soft saturation characteristicso that lingering ion current from large depositions doesnot severely inhibit double pulse resolution. Ion tailcancellation is followed by a multi-pole shaping blockto provide noise ltering without compromising doublepulse resolution. The signal at the output of the shaperis limited to about 120fC of equivalent input charge, thelargest allowable threshold setting. A baseline restorerBLR is included to eliminate eects of pileup, reducesensitivity to mismatch in the ion tail compensation anddecouple the DC osets in the preamplier and shaperfrom the comparator section.A low and high level comparator on each channelallows the ASIC to trigger on the earliest arrivingclusters from tracks for optimal position resolution andto detect energetic TR photons with high eciency. Thepeaking time of the signal into the low level or trackingcomparator is 7.5ns, chosen to optimize tradeos betweensignal to noise and tracking resolution. The high level,TR photon discriminator, has a longer, 10ns, peakingtime to allow the prompt and reected signal from theunterminated straw to be integrated. This reduces theamplitude dependence on the position of the chargedeposition along the wire, increasing the threshold deadband between ionized track depositions and TR photons.The output of the two comparators is summed as adierential current that forms a ternary output level of 0,200 or 400 A. A more detailed described of each blockmay be found in reference [2].C. MeasurementsMeasurement of the rst version of the ASDBLRpointed to the need for an increased gain (40%) in theBLR and a reduced shaping time. This was due tothe realized gain of the straw and fabricated amplier,combined with a minimum signal size requirement in theBLR for low signal attenuation. Taking advantage ofFigure 2: Measurements of the revised ASDBLR triggering at10MHz induced by distributed Sr90 sources.provisions made for metal layer revision, we were able touse wafers held at pre-metalization from the rst run tofabricate parts with the revised design parameters. Thisrevised design has been measured extensively and meetsall basic design requirements.High rate operation has been measured with Argon andXenon based gas mixtures. Figure 2 shows a scope plotof the rst high rate operation of the ASDBLR attachedto a straw module. The upper trace in the scope plotshows the analog monitor of the BLR output and thelower trace shows the ternary comparator output fromthe same channel. The straw was irradiated by severalSr90 sources achieving an eective rate of 10MHz. Nobaseline shift was observed. The operation of the ternaryoutput is demonstrated in the last time division where thea discriminator trigger of twice the standard amplitudesignals detection of an input pulse above the low and thehigh threshold levels.Test beam measurements (Summer 1998) were takenat the CERN H8 beam line using a silicon-strip detectortelescope sandwiched around a straw module to measuretrack position. Radioactive sources were added to studyrate dependence. Track resolution and eciency weremeasured at rates up to 20MHz using both the ASDBLRand a carefully tuned, DC coupled, single channel ofdiscrete electronics. A comparison of the measurements is1201401601802002202402600 5 10 15 20 25Drift-time accuracyDC-coupled, 200 eVASDBLR, 170 eVASDBLR, 266 eVRate (MHz)Drift-time accuracy (µm)30405060708090100EfficiencyEfficiency (%)Figure 3: Test Beam measurements comparing the performanceof the ASDBLR at two dierent gas gains and a hand tuned,DC coupled, single channel of discrete electronics. Note thatthe eciency in the plot is dened as a hit withing 2 of anassociated track.shown in Figure 3. With the gas gain set to its nominalvalue, the lowest operational threshold was 266eV . Atthis value, the ASDBLR oered slightly poorer trackresolution than the hand tuned electronics channel.Raising the gain by 50% improved the performance tobetter than that of the hand tuned channel suggestingthat a higher internal gain before the BLR might helpimprove track resolution.As the size and complexity of high energy physicsdetectors has grown there has been an increasing relianceon simulation tools to predict the detailed performanceof high rate detectors. In Figure 4 the predictions of amontecarlo tool developed specically for the TRT thatincludes the eects of the baseline restorer overshoot arecompared with data measured in the test beam using thefabricated ASDBLR.D. ASDBLR in Rad Hard BiCMOSSignicant overhead in the power and connectionsbetween the analog front end and the digital timemeasurement chip could be eliminated by the use of aradiation hardened BiCMOS process. We are evaluatingthe risks and benets of using a relatively new SOIprocess, DMILL.1) Prototype VersionIn June 1997 we submitted a prototype six channelASDBLR with three channels of Xenon and three channelsof Argon tail compensation in this process.A key part of this submission was the implementationof a new baseline restorer circuit. In this design, theshaper output is capacitively coupled to the BLR asbefore, but the simple diode shunt across the couplingcapacitors is replaced by a four diode bridge. Theimpedance between the outputs is regulated by adierential pair that controls the current in the bridge.When the signal is of the desired polarity, the current is0.60.70.80.910 5 10 15 20Simulated efficiencyMeasured efficiencyRate (MHz)EfficiencyFigure 4: Triggering Eciency for hits within 2 of thereconstructed track (The raw hit eciency at 0 MHz is 97%).Good agreement is shown between test beam data and asimulation tool that predicts tracking eciency for straw tubesbased on characteristics of the tube and shape of the ASICsignal at the on chip comparator input. This tool will beemployed in Monte-Carlo predictions of detector performance.reduced to near zero, increasing the impedance of thebridge to minimize the discharge of the BLR couplingcapacitors. As the shaper output returns to baselinedroop in the coupling capacitors causes the BLR output toovershoot. The current regulator shifts more current intothe diode bridge which quickly equalizes the voltage of thecoupling capacitor outputs. The shaper and BLR responseof the new circuit to a 2fC (200eV) input signal is plottedin Figure 5. In Figure 6 the advantage of the bridge overFigure 5: The above traces show the Shaper and BLRresponse as calculated by HSPICE for a 2fC (200eV equivalentdeposition) parameterized TRT pulse into an ASD with bridgetype BLR.the shunt BLR is demonstrated over a large part of theexpected operational range. SPICE calculations of gainand maximum overshoot are plotted for each BLR typeover a range of input charge from 200eV to 8KeV . Thebridge BLR gain is nearly uniform down to the 200eV ,threshold level, inputs. Fabricated parts demonstratedBLR GAIN  .VS.  INPUT CHARGEBLR OVERSHOOT RATIO .VS. INPUT CHARGEKeVKeVBridge BLRShunt BLRShunt BLRBridge BLR0 20 40 60 8000.10.20.30.40 20 40 60 800.50.60.70.80.91Figure 6: Comparison of overshoot and gain of the bridgeand shunt type Baseline Restorer as a function of input charge.high yield and good uniformity, but also indicated thatthe process was not yet mature. The resistors measured25% higher than nominal and we observed a tendency forharmonic oscillation. Nonetheless, the fabricated ASICprovided useful measurements for all aspects of operation.Figure 8 shows the shape of the TRT straw signal atthe input to the ASDBLR in the upper trace and theprocessed signal after tail cancellation observed at themonitor output in the lower trace.Although the preamp and shaping section circuitconguration is virtually identical to that of our previousdesign, we have observed high frequency harmonics in theDMILL prototype that are not present in either of twopredecessor designs manufactured in an analog bipolarbulk silicon process. In these designs, the tail cancellationstage is dierential, with each input connecting to one ofthe preampliers. Tail cancellation depends on a sharpdierentiation of the input signal which is accomplishedusing a large capacitor at the emitters of a dierentialtransistor pair. One side of this capacitor is exposed to theSHAPING ELEMENTSBACK SUBSTRATEACTIVE INPUTUNUSED INPUTDUAL PREAMPS                FIRST SHAPING STAGETOP SIDEFigure 7: The gure above depicts the model used for SPICE calculations of the eects of charge coupled to the uncommittedsubstrate below the insulator layer for the ASDBLR preamplier fabricated in the DMILL SOI process. An important elementis the capacitor between the emitters of the dierential pair. A pulse applied to the unused preamp input generates a signalon the top side of the capacitor and does not produce additional harmonics in the output. A pulse applied to the active input does.20mV X 20nsFigure 8: The upper trace is the recorded signal from a pulserdesigned to mimic the shape of point ionizations in a TRTstraw lled with a Xenon based fast gas. As can be seen in theplot, there is still appreciable current owing 180ns after thepulse. The response of the prototype DMILL ASDBLR aftertail cancellation is shown in the lower trace. Considering thefact that the process resistors were 25% above their nominalvalue, the circuit for shortening the ion tail appears to be quiterobust.back substrate and carries the amplied signal from theactive input. The other side faces away from the substrateand carries the amplied signal from the unused input.In the DMILL SOI process, the relatively low resistanceback substrate can not be directly contacted through the450nm insulator layer and is oating. We found that theharmonics observed in the prototype are consistent withcapacitive coupling from the tail cancellation circuit tothe inputs through the back substrate (see Figure 7).Pulser studies showed that when the hookup capacitanceat the inputs is unbalanced, as will be the case whenattaching to a TRT straw, harmonics are observed at theanalog monitor output when a signal is applied to theactive input, but not when an inverted polarity input isapplied to the unused input.The left plot in Figure 9 shows two measurementstaken with a digital oscilloscope. In the upper trace, apositive pulse is injected into the unused input and in thelower trace a negative signal was injected into the activeinput. Similar behavior is demonstrated in the plot onthe right side of Figure 9 using the simple SPICE modelshown in Figure 7. The external capacitance at the inputsis unbalanced (5pF and 17pF) and a 100fF capacitancecouples each input to the uncommitted substrate node.One plate of the tail cancellation capacitor couples to theback substrate with 300fF.2) Engineering VersionWe recently submitted an extensively revised andoptimized version of the ASDBLR in the DMILL processthat should meet or exceed the signal processing goalsof the TRT readout. Each channel has approximatelysix hundred hand sized and placed components. SPICEbased performance calculations were aided by the use ofsubstantially more sophisticated models of the DMILLprocess revised to include the predictable parasitic2 0 m V  X  2 0 n sFigure 9: Left Figure: The signal at the shaper monitor point of the DMILL ASDBLR exhibits an input and load-dependentharmonic pickup. In the upper trace a positive pulse is injected into the unused input, in the lower trace a negative pulse (strawpolarity) is injected into the active input.Right Figure: The results of a SPICE calculation with 100fF feedback from a global substrate node to the inputs. The plotsshow the calculated response at the shaper output with a positive signal into the unused input in the top plot and a negativesignal into the active input in the lower plot.The capacitive load on the unused input is much lower than on the active input in all cases above.capacitance to the back substrate. The calculated powerdissipation is 36mW/channel and the RMS equivalentinput noise is 2000e. Several changes to the prototypedesign were employed to reduce the susceptibility topickup from the back substrate. These include: 1)the installation of a grounded guard ring around inputdevices, 2) connection of unused silicon on the top sideof the insulator to a xed potential 3) the addition ofa low gain dierential stage to symmetrize the preampsignal before tail cancellation, 4) splitting of the tailcancellation capacitor into two half size capicators crosscoupled, 5) the use of two terminal pad structures thatprovide contact to a conductive buried layer just abovethe insulator to shield the signal on the pad from thesubstrate below the insulator. Important features of thissubmission are: Dual inputs with negative Input Protection usingNPN transistors for fast response. Digitally selectable Xenon or Argon based ion tailcancellation. Digitally adjustable tuning of the ion tailcancellation to accomodate a change in gas mixtureor wire diameter. Bridge type baseline restorer Two level discrimination: Low level- 7.5ns peakingtime, 0-10fC range. High Level- 10ns peaking time,15-120fC range. Programmable current ternary output 0 - 3mA steps(200uA design) Analog monitor of the input and output to thebaseline restorer on channel 1 and 8.This chip was designed for use with a partner chip,the DTMROC, which will decode the ASDBLR ternaryoutput, register the time of leading and trailing edges oflow level triggers as well as indicate the presence of a highlevel trigger (suggesting the presence of a TR photon).I. References[1] ATLAS TDR 4 CERN/LHCC/97-16, ISBN92-9083-102-2, April, 1997.[2] B. Bevensee, F.M. Newcomer et al. An AmplierShaper Discriminator with Baseline RestorationIEEE Transactions on Nuclear Science, 1996, V43 Pg.1725.

Progress in development of the ASDBLR ASIC for the ATLAS TRT

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