Cantatore, E

Corsi, F

Marzocca, C

Matarrese, G

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RELATIVE ROBUSTNESS AGAINST PROCESS FLUCTUATIONS OFBASIC BUILDING BLOCKS FOR ANALOG FRONT-END OF PARTICLEDETECTORSE. Cantatore*, F. Corsi°, C. Marzocca°, G. Matarrese°* CERN, Geneva, Switzerland° Dipartimento di Elettrotecnica ed Elettronica, Politecnico and Sezione INFN di Bari, ItalyContact: C. Marzocca (email: marzocca@poliba.it)AbstractThe large number of channels (15.7 millions), neededfor the silicon pixel detector under development for theALICE ITS, requires a careful study of the statisticalfluctuations of the front-end electronics performance.By means of classical techniques, such as thePrincipal Component Analysis, and of new ones used toperform a “realistic” worst case analysis, variousconfigurations of basic CMOS amplifier stages havebeen compared to evaluate the relative robustness oftheir performance against manufacturing fluctuations.To validate the simulated results on a significantstatistical sample, a test pattern containing these basicbuilding blocks has been designed and implemented in a0.35µm process. In this work we present the theoreticalresults, achieved by applying the proposed Worst CaseAnalysis technique. The characterisation of the test chipprototypes is currently in progress.1. INTRODUCTIONIn the Alice Inner Tracking System (ITS) a very largenumber of pixel channels is required to ensure theneeded resolution. As a consequence, a high degree ofuniformity between pixel front-end cells is mandatory toreduce channel to channel threshold dispersion,optimise time-walk performance at the system level, andguarantee shaping time accuracy and an acceptableproduction yield. [1]The non-uniformity of the performances of the front-end electronics blocks is basically due to technologicalprocess variations, such as fluctuations of the oxidethickness and of the charge trapped in the oxide. Theseprocess fluctuations induce corresponding variations inthe device parameters.A large amount of preliminary work is needed toperform any statistical analysis of a circuit.Since the process fluctuations are described in termsof variations in the device parameters, the choice of thedevice model and of the parameter extraction proceduredeeply affects the results of the analysis. We will use thePhilips MOS Model 9 [2], which guarantees accuratemodelling of transistors manufactured in recent sub-micron technologies,  but  involves many optimisationsteps in the extraction process. These must be performedvery carefully in order to obtain optimal extractionrepeatability and have a good estimate of the physicalparameter statistics [3].Another issue to be addressed in the statisticalcharacterisation of devices is the choice of the size of theMOSFETs to be measured to characterise thetechnology. In fact the extracted parameters accuracyoften depends on the transistor dimensions [4]. A largenumber of both PMOS and NMOS devices must then beavailable in order to achieve statistically significantresults, especially when studying the parametercorrelation.Finally a sensitivity study of the circuit performancesto the varying model parameters should also be done, inorder to choose the most significant parameters for thestatistical analysis.In our work, we focus on worst case analysis of basicbuilding blocks for analogue front-end of particledetectors.First a review and comparison of classical statisticaltechniques for worst case analysis is presented in orderto assess the required computational effort and theimpact of correlation between parameters on the results.Then we describe a new technique for a “realistic”worst case analysis which preserves correlation betweenparameters and presents a limited computationalcomplexity [5].After validating the proposed technique by comparingits results with those provided by an extensive MonteCarlo analysis carried out on a digital inverter, weapplied it on a set of basic amplifier stages such as astraight cascode, a folded cascode, and a simple OTAwith active load, in order to compare the relativerobustness of some of their performances, such asvoltage gain and output offset.Furthermore a test chip containing the whole set of theconsidered building blocks has been designed andimplemented in a 0.35µm CMOS process, to verifyexperimentally the results achieved.2. STATISTICAL TECHNIQUES2.1  Traditional Monte Carlo analysisThe first step is to consider the traditional MonteCarlo analysis. In this technique, a set of NMOS andPMOS parameters is calculated for each iteration, on thebasis of their mean value and standard deviations, byusing a unit normal random number generator. A circuitsimulation follows. Repeating this procedure astatistically meaningful number of times, the statisticaldescription of the circuit performances is obtained. Thevariability range of each parameter is fixed to ± 3σ withrespect to its mean value.The major problem connected to this procedure is thatcorrelation between parameters is not taken into accountand this causes the performance worst case estimation tobe too pessimistic.Furthermore when only a worst case analysis isrequired, this technique is too computationally expensiveand time-consuming.2.2  Principal Components AnalysisIn order to preserve correlation between deviceparameters both of the same and of the different channelkind, the well-known Principal Component Analysis hasto be carried out. It consists in finding a set of linearequations that express the normalised model parametersas a combination of independent unit normal randomnumbers (Principal Components) [6,7]:P’ = U Λ0.5 C (1)where P’ is the normalised model parameter vector, C isthe principal component vector, while Λ and U arerespectively the eigenvalues and the eigenvectorsmatrices of the parameter correlation matrix.The variability of each parameter is expressed throughthe well known statistical model, presented in eq. 2[6,7]:P= µprocess(P)+σinter(P)Rinter(P) (2)Eq. 2 expresses the inter-die variability of the genericparameter P. The unit normal random number Rinter isobtained from equation (1) and preserve correlationbetween parameters. The principal components can begenerated independently by a random number generator,and by using eq. (1) and (2), a set of device parameterscan be obtained for each iteration.Monte Carlo analysis following this scheme (PCAMonte Carlo) yields more realistic results than thetraditional Monte Carlo, but is still too complex a way toobtain a worst case estimation.In fig. 1 a comparison between traditional and PCAMonte Carlo analysis is shown for a CMOS inverter,while table 1 and table 2 reports respectively the averagevalue and the standard deviations used for theparameters and their correlation coefficients. In this caseonly the threshold voltages and the transconductanceparameters for NMOS and PMOS transistors have beenconsidered.Table 1. Statistical properties of the parametersemployed in the Monte Carlo analysis of a CMOSinverter.Parameter Mean St. Dev.Vtp -0.789 1.54 E-2Vtn 0.672 3.40 E-3βp 392 E-6 4.18 E-7βn 567 E-6 1.25 E-6Table 2. Parameter correlation matrix.Vtp Vtn βp βnVtp 1 -0.2 0.9 0.3Vtn -0.2 1 -0.3 -0.1βp 0.9 -0.3 1 0.4βn 0.3 -0.1 0.4 1Fig. 1. DC characteristics for a CMOS inverter:traditional Monte Carlo curves (grey lines) and PCAMonte Carlo curves (black lines). It is clear from fig. 1 that the DC characteristicsspread is reduced by the correlation between parameters,and that the traditional Monte Carlo Analysis providespessimistic and meaningless worst case  results.Vout [V]Vin [V]PCA MCworst case MCworst case2.3  Traditional Worst Case AnalysisAccurate worst case analysis can, of course, beperformed by an extensive (more than 2000 simulations)Monte Carlo analysis. It is sufficient to calculate, foreach circuit performance, its ± 3σ values with respect toits mean value. But for a simple worst case analysis, acomplete Monte Carlo simulation is too time-consuming.It would be better to find directly the “corner points” inthe parameter space that correspond to the performanceworst case values. A very simple way to try to do this isto run circuit simulations with all the device parametersset to their ± 3σ values, including all the possiblecombinations.This procedure is based on the assumption that thefunction that maps the device parameters space to thecircuit response space must be approximatelymonotonic, otherwise it is not possible to find theperformance corner points starting from the deviceparameter ones [8].“Approximately monotonic” means that the mappingfunctions can have some ripples, but such ripples mustbe small respect to the full range of variability [8]. Astudy of the circuit performance sensitivity to the deviceparameters can be performed to verify this assumption,and to determine the worst case directions for eachparameter [9].The worst case analysis carried out with this simpleprocedure leads to very pessimistic estimation of thecircuit performance corner points. This happens becausecorrelation between parameters is not taken into accountso that the corner points chosen in the device parameterspace are not physically meaningful.3. PROPOSED WORST CASETECHNIQUE3.1  PCA Worst Case AnalysisThe technique we propose, which we call PCA worstcase analysis, preserves correlation between parameters.The starting point is to perform a Principal ComponentAnalysis, in order to relate the vector of the n normalisedparameters to the unit normal random vector of principalcomponents. Then one parameter is fixed at its upper orlower bound (± 3σ), and a set of principal components iscalculated, which provides the chosen value of theparameter.For instance, for the parameter P1 set at its +3σ value,if the correspondent expression in function of theprincipal components is:P1 = A1 C ,                          (3)where vector A1 is the first row of the matrix UΛ0.5.We can writeC = (A1)-1 3σ                      (4)The extraction of this vector C is performed by meansof a least square method based on the pseudo-inversionof the matrix A1 [10]: in this way the chosen vector ofprincipal components C has minimum norm. Thisimplies that the extracted vector is also the most likely tooccur among the ones which provide P1=3σ.The values of the remaining parameters Pj, j≠1, arethen calculated on the basis of the chosen vector ofprincipal components, through equation (1).3.2  Example: comparison of different analysismethods for a CMOS inverterIn order to test the effectiveness of this technique anextensive PCA Monte Carlo simulation has been carriedout for a simple CMOS inverter (2000 iterations). Then aworst case analysis has been implemented with both thetraditional technique and the proposed one. Fig.2 andfig.3 represent respectively the input-output DCcharacteristics Vout – Vin and the supply currentcharacteristics Id – Vin. In table 3 a comparison of themaximum relative dispersions provided by the threemethods is reported for some of the main circuitperformances, such as the input offset, the inversionvoltage, the gain and the noise margins.Fig. 2. DC Vout/Vin characteristics for a CMOS inverterFig. 3. DC Id/Vin characteristics for a CMOS inverterProposed worst caseTrad. worst caseProposed worst caseTrad. worst caseTable 3. CMOS inverter: comparison between differentanalysis methods.Performancerelativevariations [%]PCAMonteCarloProposedWorstCaseTraditionalWorstCaseInput offset 4,96 3,60 7,66Inversionvoltage4,48 3,13 7,61Gain 5,38 4,03 7,29High noisemargin9,81 7,93 15,45Low noisemargin12,23 10,91 20,91Fig. 4. Gain histogram of a CMOS inverter, obtainedwith 2000 PCA Monte Carlo simulations. The worst caselimits, obtained with the proposed PCA worst caseanalysis (PCA WC) and with the simple worst caseanalysis (Trad WC) are also plotted.In this example the Principal Component Analysis hasbeen performed on a total of 20 parameters (10 for theNMOS and 10 for the PMOS device) and using 20principal components. The Philips Model 9 parametersconsidered are: the threshold voltage Vto, the gain factorβ, the mobility reduction coefficients θ1, θ2, θ3, the bodyeffect parameter k, the sub-threshold region parametersmo, ζ1, the output conductance related parameter γ1, andthe channel length modulation characteristic voltage Vp.Since a traditional Worst Case Analysis with 20varying parameters can not be performed because of thehigh number of possible combinations of parameters setto their ± 3σ values (220), in our analysis the number ofparameter combinations has been reduced by means of apreliminary sensitivity study, whose main aim is to showwhich parameters the circuit performances are mostsensitive to.It is evident from table 3 that the circuit performancespreads evaluated by means of the proposed worst caseanalysis technique are closer to those obtained by a PCAMonte Carlo than the ones calculated with a traditionalworst case analysis.In fig. 4, a gain histogram obtained with the PCAMonte Carlo simulations is presented, together with theworst case limits obtained with both the traditional worstcase technique and the proposed one. The performancelimits provided by the PCA worst case analysis areestimated to be about a factor 2.5 the standard deviationsforeseen by the PCA Monte Carlo, whereas the results ofthe traditional worst case technique are evidentlyunrealistic. Thus the estimation of the worst case circuitperformances obtained from the proposed technique isjust a little less conservative than the one provided byPCA Monte Carlo. This is caused by the use of theminimum norm vector of principal components whichresults from the above mentioned pseudo-inversion ofthe matrix UΛ0.5 rows. In fact more vectors of principalcomponents may exist which give the same ± 3σ valueof the current parameter and have not negligibleprobability of occurrence, even though their norm isnon-minimum. These vectors are neglected in our worstcase analysis.4.  COMPARATIVE WORST CASE STUDY     OF ANALOGUEBUILDING BLOCKSAfter validating the proposed worst case technique ona CMOS inverter, we applied it to compare theperformances of three basic amplifier stages: a straightcascode, a folded cascode, and an OTA with active load.All the circuits share the same nominal gain value.Fig. 5.  Layout of the OTA stage, showing the NMOStransistors with enclosed structure.Simulations on these basic analogue stages have beencarried out considering the corner points in the deviceparameter space found by means of the PCA worst caseanalysis, as described in the previous section.Three performances have been chosen to comparethese circuits: the output offset, the voltage gain and thebandwidth. In table 4 the simulation results have beenreported.The OTA with active load exhibits the best results forall the considered performances. This is due to theexistence of an intrinsic feedback and to the balancedstructure of the circuit. The current mirror used as activeload tends to make equal the currents in the twobranches of the circuit and improves the robustness ofthe stage against the inter-die parametric variations. Thefolded cascode shows better behaviour compared to thestraight version of the circuit. This can be explainedconsidering that in the folded structure the mainperformances of the circuit depend on parameters ofMOSFETs of the same kind (NMOS or PMOS), whereasin the straight structure the same performances exhibitdependence on parameters of both NMOS and PMOSdevices.Table 4. Comparison of the performance relativevariations for three basic amplifier stages.Performancerelative variations[%]StraightCascodeFoldedCascode OTAOutput offset 54,01 47,71 32,31Voltage gain 6,95 2,29 0,29f-3db 34,20 11,15 5,63It must be pointed out that in all the simulations ofboth versions of the cascode, the reference voltages havebeen implemented by means of simple CMOS biasingstructures instead of ideal voltage sources, since in realcircuits this is the most used solution. If the referenceswere realised with independent voltage sources, theresults reported in table 4 would be quite different.5.  CONCLUSIONSA novel technique for a realistic worst case analysis ofanalogue building blocks has been presented. Theproposed method preserves parameter correlationwithout requiring excessive computational effort. Thismakes it suitable to perform the statistical analysis oflarge circuits instead of a time-consuming Monte Carlosimulation carried out together with the PrincipalComponents Analysis.The technique has been applied to a set of basicCMOS building blocks, such as the straight cascode, thefolded cascode, and the OTA with active load, to assesstheir relative robustness against the process inducedparameter fluctuations. The results obtained are referredto a set of performances usually relevant in the design offront-end circuits. The relative degree of robustness ofthe examined stages is likely to hold even for differentstatistical input data, while this is not guaranteed if adifferent choice of the considered performances is made(noise, linearity, etc.). Therefore it is up to the designerthe proper choice of the specs to be considereddepending on the particular application. Here weintended to propose a technique to make viable theevaluation of the performance spread for circuits ofrelatively high complexity, such as those encountered inactual front-end channels.6.  REFERENCES1. E. Cantatore, M. Campbell, et al., “Statisticalanalysis and optimization of delay line chains forpixel readout electronics”, Nucl. Instr. and Meth. inPhys. Res. A 395 (1997) pp. 318-323.2. R.M.D.A. Velghe, D.B.M. Klaassen, F.M. Klaassen,“MOS Model 9”, Philips National LaboratoryUnclassified Report NL-UR 003/94.3. M. Bolt, E. Cantatore, M. Socha, C. Aussems and J.Solo, “Matching Properties of MOS Transistors andDelay Line Chains with Self-Aligned Source/DrainContacts”, Proceedings of the ICMT’96, Trento –Italy (March 1996).4. E.V. Saavedra Diaz, K.G. McCarthy, D.B.M.Klaassen and A. Mathewson, “Efficient parameterextraction and statistical analysis for a 0.25 micronlow-power CMOS process”, Proceedings of the 27thEuropean Solid-State Device Research Conference(ESSDERC’97), pp. 656-659, Edition Frontiers,1997.5. M. Bolt, M. Rocchi, and J. Engel, “RealisticStatistical Worst-Case Simulations of VLSICircuits”, IEEE Trans. on SemiconductorManufactoring, vol. 4, n. 3, August 1991, pp. 193-198.6. C. Michael, M. Ismail, “Statistical modeling forcomputer–aided design of MOS VLSI circuits”,Kluwer Academic Publishers Boston/Dordrecht/London.7. C. Michael, M. Ismail, “Statistical modeling ofdevice mismatch for analogueMOS integratedcircuits”, IEEE Journal of Solid State Circuits, vol.SC-27, February 1992, pp. 154-166.8. D. Stoneking, “Improving the manufacturability ofelectronic designs”, IEEE Spectrum, June 1999, pp.70-76.9. S. R. Nassif, A. J. Strojwas, and S. W. Director, “AMethodology for Worst-Case Analysis of IntegratedCircuits”, IEEE Trans. on Computer-Aided Design,vol. cad-5, n. 1, January 1986, pp. 104-112.10. D. Bini, M. Capovani, O. Menchi, “Metodi numericiper l’algebra lineare”, Zanichelli Bologna, 1988, pp.456-462.

Relative robustness against process fluctuations of basic building blocks for analog front-end of particle detectors

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