Abbrescia, M

Altieri, S

Belli, G

Bruno, G

Colaleo, A

Gianini, G

Guarrasi, L

Iaselli, Giuseppe

Loddo, F

Maggi, M

Marangelli, B

Natali, S

Nuzzo, S

Pugliese, G M

Ranieri, A

Ratti, S P

Riccardi, C

Romano, F

Torre, P

Viola, L

Vitulo, P

CERN Document Server

A PROTOTYPE FRONT END CHIP FOR THE CMS RESISTIVE PLATECHAMBERSM. Abbrescia, A. Colaleo, L. Guarrasi, G. Iaselli, F. Loddo, M. Maggi, B. Marangelli, S. Natali,    S.Nuzzo, G. Pugliese, A. Ranieri, F. RomanoDipartimento Interateneo di Fisica and Sezione INFN, Bari, ItalyS. Altieri, G. Belli, G. Bruno, G. Gianini, S. P. Ratti, C. Riccardi, P. Torre, L. Viola, P. VituloDipartimento di Fisica Nucleare e Teorica and Sezione INFN, Pavia, ItalyAbstractA new front-end amplifier-discriminator-monostableintegrated circuit for the CMS Resistive Plate Chambers ispresented.The aim of the circuit is to amplify current signals,ranging from 20 fC to 20 pC and generate output pulseshaving rise time as fast as possible for timing purposes.The full custom ASIC was designed and manufactured inthe 0.8 mm BiCMOS technology by Austria MikroSysteme.1. INTRODUCTIONThe Resistive Plate Chambers are gaseous parallel-platedetectors that will be used in the CMS experiment for themuon trigger system [1]. In fact they combine goodspatial resolution with an excellent time resolution andmake the muon trigger capable of identifying muon track,measure its transverse momentum and relate it to thecorrect bunch crossing.The RPC proposed for CMS consists of two 2-mm gapswith common pick-up readout strips in the middle andwill be operated in the so-called avalanche mode, forsustaining event rates up to 1000 Hz/cm2. The shape ofthe current signal, induced by a single cluster, is describedby the function I(t) = I0exp(t/t), 0 £ t £ 15 ns, for freon-based gas mixtures having electron drift speed in the orderof 130 mm/ns and t (gas time constant) ~ 1 ns at thenominal working point of the detector. This can also beconsidered a good approximation of the real signal, sincealmost the whole-induced current originates from the firsttwo clusters.2. DESIGN CONSTRAINTSIn the barrel RPC, the readout strips are 1.3 m long,with a propagation delay ~ 5.5 ns/m while their widthranges between 2 and 4 cm, according to RPC position inthe apparatus. The characteristic resistance of the stripranges from 40 to 15 Ohm respectively, while theircapacitance ranges between ~160 pF and ~ 420 pF.  Theinduced signal has a rise time (~ 1ns) shorter thanpropagation delay of the strip, therefore this one behaveslike a transmission line and must be properly terminated atboth ends. In fact, reflected signals increase occupancyand, if the termination resistance is larger than thecharacteristic resistance of the strip, a fraction of inputcharge is reflected and lost. The strip is terminated on oneend by the input resistance of preamplifier, on the otherend by a resistor.Simulations and past experience show that, setting thethreshold around 20 fC, the detector is fully efficient. Thismeans that a snoise< 4 fC could be tolerated.3. CIRCUIT DESCRIPTIONThe circuit is made of eight identical channels, each oneconsisting of amplifier, zero-crossing discriminator,monostable and differential line driver. A single channelblock diagram is shown in Fig.1. Since the terminationresistor has a small and variable value, an AC couplingbetween strip and amplifier is required. The requested power supplies are +5V and GND; theoverall power consumption is about 45 mW/channel.InVtest PreamplifierDummy PreamplifierGain stageVbias Vth VdriveZero-crossingDiscriminatorOutpOutmDriverVmoMonostable   Fig.1. Single channel block diagram3.1  The AmplifierThe preamplifier (Fig. 2) is a cascoded common emittertransresistance stage, with input impedance of 15 Ohm atthe signal frequencies (between 100 MHz and 200 MHz),in order to match the characteristic impedance of the stripin the worst case of 4-cm wide strips. In the other cases,the matching will be obtained adding an external seriesresistor at board level. The current in the input transistorQin is about 700 mA (for noise reason, as shown in §3.2)and, in order to reduce the supply voltage value [2], aresistor Rcasc is added between the emitter and the base ofthe cascode transistor Qcasc. The value of Rcasc is about 4.5kW  that is much higher than the input impedance of Qcascand only a small fraction of the signal current is lost intoRcasc. The open loop gain is about 100, while the dominantpole is about 116 MHz and the charge sensitivity is 0.5mV/fC. A “dummy” input preamplifier was required tobalance the DC output variations of the real input firststage.          RloadRcascVcasc QcascVtest CtestInRfeedCfeedVoutQinFig. 2: Current PreamplifierThe expression of the input admittance is:÷÷øöççèæ++÷÷øöççèæ++=loadloadloadmfeedfeedini CsRRgsCRsCsY111)( (1)where Cin is the input capacitance of Qin; Rfeed and Cfeedare, respectively, the feedback resistance and capacitance;gm~ 27mA/V is the transconductance; the parallel of Rloadand Cload is the internal load across which the voltage gainis produced.If we set RloadCload = RfeedCfeed and define Ctot= Cin+Cfeedthen feedloadmtoti RRgsCsY +=)( (2)If we impose W== 15loadmfeedin RgRR , thentotinini CsRRsZ+=1)( (3)Being Ctot < 3pF, the pole of the above expression is > 1GHz and Zi  ~ Rin ~ 15 Ohm (4)up to the signal frequencies (between 100 MHz and 200MHz), as required by the matching condition.    Inp InmQ1HQ1L Q2LQ2HRL RLRe ReVbiasOutpOutmRp1Rp2Rp1Rp2Fig. 3: Gain stageThe preamplifier is DC-coupled to a gain stage, whoseschematic is shown in Fig. 3. It is designed to providenon-saturated response on the dynamic range and to fullyexploit the zero-crossing timing, as shown in §3.3. Thecircuit must ensure a linear behaviour only in thethreshold range (Qin < 100 fC), while for larger inputsnon-linearity is not a problem. A simple way to meet theserequirements is to design a two-step piecewise-linearfunction fitting, which is accomplished by summing theoutput currents of two gain segments. The preamplifieroutput is sent to two differential amplifiers havingdifferent gains but common output nodes. The externalamplifier (Q1H, Q2H, RL) has a DC voltage gain ~ 7 and isused to amplify small signals (Qin < 200 fC) while theinternal one (Q1L, Q2L, RL) has a voltage gain ~ 0.25 andamplifies signals above 200 fC never saturating in thedynamic range. The overall charge sensitivity is 2 mV/fCfor input charges < 100 fC and the power consumption ofthe amplifier, including the “dummy stage”, is 15 mW.The transfer characteristics of the amplifier are shown inFig.4, while a typical transient response is shown in Fig.5.2k 4k 6kQ (fC)Vout (mV)06005004003002001000Fig. 4: Transfer characteristics of the amplifier(V)(V)(A)Time (s)Input current pulse (Q = 50 fC)Differentiated amplifier outputGain stage outputFig. 5: Typical amplifier output3.2 Noise calculation The equivalent circuit of RPC and amplifier for noiseanalysis is shown in Fig.6 [3].The parallel noise is dominated by the thermal noise ofthe terminating resistor R0 at the far end of the strip andcan be represented by an equivalent noise currentgenerator with power density i2n (A2/Hz) in parallel to R0:i2n = 4KT/R0  ~ 1.1*10-21  A2/Hz  (T = 300 K) (5)The series noise is represented by an equivalent noisevoltage generator with power density e2n (V2/Hz) in serieswith the input:e2n = 4KT (0.5/gm + RBB’) ~ 4.9*10-19  V2/Hz(6)being RBB’ ~ 11 Ohm the base spread resistance of Qin.i2n R0 Ctote2nRi VoutH(s)R0, t0IinZZ1R0Fig. 6.   Equivalent circuit of RPC and amplifier for noiseanalysis.The preamplifier is current sensitive, so it is convenient totransform the noise voltage generator into an equivalentcurrent noise generator with power spectrum        (7)where 0001RCsRRZtot»+=  is the impedance shown inFig.6, assuming the strip impedance matched at the farend. For simplicity, assuming Rin ~ R0 = 15 Ohm, asshown in the expression (4), we obtain:ieRn sn22024= = 5.5 *10-22 A2/Hz (8)The rms noise at the output is found by integration of thenoise current through Rin multiplied by the square of themagnitude of the amplifier transfer function H (jw):V i H j dfns ns=¥ò 202( )w  ~ 2.1 mV rms (9)where LinoutsAsIsVsHt+»=1)()()( (10)being tL the time constant of the dominant pole and A thegain. Assuming the line to be ideal, the impedance seen atthe far end is:)tanh()()tanh()()(000001 stsZRstRsZRsZii++= , (11)being t0 ~ 7 ns  is the propagation  delay and Zi theexpression (3). Then, the parallel noise current flowinginto the preamplifier is:210022ZRRii nnp+= (12)If we assume again Zi = Rin = R0, then Z1 = R0 and422 npnii = = 2.8*10-22 A2/Hz (13)The rms parallel noise at the output is:V i H j dfnp np=¥ò 2 20( )w  ~  1.5 mV rms. (14)Finally, the total output noise is:V V Vn ns np= +2 2 ~ 2.6 mV rms. (15)Simulations of the circuit, including all the noisesources, shows a total output noise ~ 3.4 mV,corresponding to an ENC ~ 1.7 fC, fully satisfying thenoise limit of 4 fC.3.3 Zero-Crossing DiscriminatorAccurate timing information from the RPC is crucial forunambiguous assignment of the event to the related bunchcrossing. The simplest method to provide trigger pulse isthe leading edge timing, which can be performed by athreshold discriminator. Though its simplicity, thismethod is affected by the amplitude time-walk. In the caseof RPC signals, with a 1000:1 dynamic range (20fC to 20pC), the time walk is ~ 10 ns [4].An amplitude-independent timing response can beapproximated by the technique of zero-crossing: a C-Rnetwork differentiates the input signal and produces abipolar pulse crossing the zero in correspondence of thepeak of the input signal [5]. In the hypothesis that inputsignals have the same peaking time, the zero-crossingtime is independent of signal amplitude and can be usedas time reference. This solution can be easily integratedinto ICs. In Fig. 7, the block diagram of the implementeddiscriminator is shown. The differential outputs of theamplifier are strongly differentiated through a CR networkhaving 4 ns time constant. This grants the fast recoverytime of the baseline (< 50 ns) as shown in Fig. 8.InpInmOutpOutmZero-crossingDiscriminatorVth  ThresholdDiscriminatorOne-shot  Arming pulse   Shaped Arming pulseTiming pulseCoincidence gateFig. 7: Discriminator block diagram222|| ZReiinsn +=The threshold (arming) discriminator provides chargeselection capability and consists of a double stagedifferential amplifier, with a threshold range between 5 fCand 500 fC.(V)Qin = 20 fCQin = 600 fCQin = 20 pCTime (s)Differentiated amplifier outputFig.8 Differentiated amplifier output in the dynamicrange.A one-shot circuit follows the arming discriminator. Itshapes the arming pulse typically at 20 ns, in order toensure its coincidence with the ZCD output.The zero-crossing discriminator is another double stagedifferential amplifier, having no threshold. Combining theoutput of the one-shot and that of the ZCD, we obtain theoutput of the discriminator, as shown in Fig. 9.The power consumption of the discriminator is about 8mW.3.4 The monostable and the Output DriverIn an RPC working in avalanche mode, an after-pulseoften accompanies the avalanche pulse with a delayranging from 0 to some tens of ns. Therefore, amonostable circuit follows the discriminator and gives apulse shaped typically at 100 ns, in order to mask thepossible second trigger and to prevent the zero-crossingdiscriminator from triggering on the noise. The choice ofthe pulse length comes from the trade-off between thepossible second trigger and the dead time. Being theexpected maximum rate less then 400 kHz/channel, alength of 100 ns, giving a dead time of 4%, has beenconsidered a good compromise. In any case, there is thepossibility to tune it in the range 50 ns ¸  300 ns.  Thedead time introduced by the monostable is ~ 10 ns and itspower consumption is ~ 2 mW.The Output Differential Driver is capable to feed atwisted pair cable with a signal level of 250 mV on 100W , as required by LVDS receivers. The powerconsumption is ~ 18 mW but the driver output current canbe tuned in order to compensate process variations.One-shot responseZero-crossing discriminator responseDiscriminator  response (AND output)ABA*BZero-crossingFig.9 Discriminator principles of operations.4. TEST RESULTS14 untested prototypes were received and tested in April99. They were mounted on a test board housing 2 chips.4.1 Analog performancesIn the first phase, we set the gain of the amplifiers to thenominal value of 2 mV/fC. In the chip, four channelsshare the same gain control input so we measured the gainuniformity inside each group of four channels. Themaximum spread measured was less then ±7%, for inputcharges < 80 fC.  Being the amplifier AC-coupled to thediscriminator, this spread represents also a measure of thethreshold uniformity and, for our application, it is fullysatisfying. For instance, setting the threshold to thenominal value of 20 fC, the maximum expected error isonly ±1.5 fC.The noise was measured using the following technique[6]: an input charge Qin at the frequency fin is sent to thecircuit. With the superposition of the noise, the signalamplitude has gaussian distribution; we set two differentthreshold Vth1 and Vth2 in order to have the output signalwith frequency fout1 = 0.117 fin and fout2 = 0.883fin. Then,Vth1-Vth2 = 2.35sn = 8.5 mV, corresponding to an ENC ~1.8 fC.4.2 Timing performancesTiming performances were measured using anoscilloscope HP54542C. The threshold was set to 30 fCand charge pulses ranging between 35 fC and 20 pC wereinjected by means of a pulse generator LeCroy 9210. Forall the prototypes, the maximum input to outputpropagation delay dispersion among the eight channelswas measured as shown in Fig. 10. The maximum DTresulted to be 0.9 ns.Fig. 11 shows the average delay time: for Qin < 2 pC,the time walk is less then 1.5 ns. For higher charges (up to20 pC) it rises up to 2.5 ns.00.10.20.30.40.50.60.70.80.911 2 3 4 5 6 7 8 9 10 11 12 13 14 15Chip #Tmax -Tmin (ns)Qin = 35 fCQin = 500 fCQin = 2 pCQin = 20 pCFig.10. In-chip delay dispersion.32333435363738391 2 3 4 5 6 7 8 9 10 11 12 13 14Chip #Time (ns)  (Arbitrary zero)Qin = 35 fCQin = 500 fCQin = 2 pCQin = 20 pCFig.11. Average delay time.5. CONCLUSIONSA BiCMOS front-end chip for the CMS-RPC detectorshas been designed and prototyped.  Measurements on 14prototypes agree with the simulation results and fulfil allthe design constraints.6. ACKNOWLEDGEMENTSWe would like to thank Mr. Raffaele Liuzzi for thedefinition of the test-board design, Mr. Michele Papagniand Mr. Carlo Pinto for their useful support in theelectronic set-up.7. REFERENCES[1] CMS Muon Technical Design Report (1997).[2] F.M.Newcomer et al., “A Fast, Low Power, Amplifier-Shaper-Discriminator for High Rate Straw TrackingSystems”, IEEE Trans. Nucl. Sci., Vol.40, No.4, pp. 630-636, August 1993.[3] V. Radeka, “Low noise Techniques in Detectors”,Annual Reviews of Nuclear and Particle Science, Vol.38(1988).[4] F. Loddo et al., “Front End Electronics for RPCdetector of CMS”, Proceeding of the 4th InternationalWorkshop on Resistive Plate Chamber and relatedDetectors, Napoli 15-16 October 1997.[5] M.L.Simpson et al., “An Integrated, CMOS, Constant-Fraction Timing Discriminator for Multichannel DetectorSystems”, IEEE Trans. Nucl. Sci., Vol.42, No.4, pp. 762-766, August 1995.[6] P. Jarron et al., “A fast current sensitive preamplifier(MSD2) for the silicon microstrip detector”,  Nucl. Instr.& Meth. 226 (1984) 156-162.

A Prototype front end chip for the CMS Resistive Plate Chambers

A Prototype front end chip for the CMS Resistive Plate Chambers

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