Appel, J A

Cancelo, G I E

Christian, D

Hoff, J R

Kwan, S

Mekkaoui, A

Yarema, R J

Zimmermann, S

CERN Document Server

FPIX1: an Advanced Pixel Readout ChipA. Mekkaoui, J.A. Appel, G. Cancelo, D. Christian, J. Hoff, S. Kwan,R.J. Yarema, S. Zimmermann.Fermilab∗, Batavia IL                                                          ∗ Work supported by the U.S. Department of Energy under contract No.DE-AC02-76CH03000.1. INTRODUCTIONAt Fermilab, a pixel detector for BTeV is proposedfor installation a few millimeters from the beam. Itsinformation will be used in on-line track finding forthe lowest level trigger system. This requires a high-speed readout and immediate data transfer from thepixel chip to the trigger processor. It is also believedthat a 2-4 bits of analog information is required toachieve the targeted spatial resolution [1] with 50µwide pixels.Our first prototype, FPIX0 [2], is now being used ina beam test to confirm physics simulations and todetermine the required resolution of the analog“information”.Our 2nd prototype, FPIX1, is a 160X18 pixelreadout chip compatible with the ATLAS family ofdetectors. We have build and tested 4 FPIX1-detectorassemblies. FPIX1 is realized in the HP 0.5µ process.The main features of FPIX1 are:• 2bit flash ADC on each cell for maximum speed.• Triggered or stand alone operation.• High speed sparse and time ordered Readout.2. THE FPIX1 CHIPThe FPIX1 is a column based pixel chip with 50×400 µm pixel cells arranged in an array of 160 rowsby 18 columns. FPIX1 stores hit informationawaiting readout in the pixel unit cells, and uses anindirect addressing scheme to reference the hits toBCO numbers held in registers at the end of eachcolumn.  Instead of using pointers to accomplish theindirect addressing, as in [3], FPIX1 uses a commanddriven design, which is described below. The chipcan be divided into three mutually dependent pieces:the Pixel Cell, the End-Of-Column (EOC) Logic andthe Chip Control Logic (Figure 1).The responsibility of the Chip Control Logic is tocontrol and maintain all features that are common tothe chip such as the clocks, the “current” and“requested” BC0 numbers, and the status of off-chipcommunication.  Each one of the eighteen EOCLogic cells controls one column.The EOC Logic responds to information from theChip Logic, and from the 160 pixels in a column bybroadcasting commands to the Pixel Cells, and byarbitrating with the other EOC Logic cells for controlof the on-chip data bus.  Finally, each Pixel Cellconnects to one sensor pixel and responds tocommands from the EOC Logic.  The commandsused in this architecture are the following: the “input”command instructs a Pixel Cell to accept hits from itssensor pixel and to respond to a hit by alerting theEOC.  In the absence of an input command, the hit isignored.  The “output” command instructs the PixelCell to prepare to write its information onto the bus.The “reset” command instructs the Pixel Cell to resetits contents.  Finally, the “idle” command instructsthe Pixel Cell to do nothing.To buffer for 4 hits and decrease the column deadtime, each EOC Logic cell consists of four EOCcommand Sets, each one capable of generating itsown commands.  When a Pixel Cell receives a hit, itimmediately associates itself with whatever EOC Setis broadcasting the “input” command.  From thatpoint until it is reset or output, the Pixel Cell onlyresponds to commands from its associated EOC Set.Meanwhile, the EOC Set holds the timestamp.  TheEOC Set can then issue the “output” or the “reset”command.  The hit information is stored inside thePixel Cell until readout.The Chip Command Logic supports two readoutmodes.  The first one, the “continuous” readoutmode, requires no external trigger.  This mode isexpected to be used in the BTeV experiment.  Theother readout mode is the external trigger mode, inwhich an external system must provide the timestampof the hits that should be read out.  This mode isapplicable for pixel detectors with external trigger,and for diagnostic purposes.2.1 Pixel CellsThe pixel cells hold the front-end electronics and thedigital interface with the EOC Logic.The FPIX1 front-end is based on a designimplemented in the FPIX0 and Pre-FPIX1 test chips.References [2,4] report in detail on measurements ofFPIX0, both unbonded and bonded to an ATLAS testsensor.  The front-end (Figure 2) contains a chargesensitive amplifier (CSA) and a second amplificationstage.  The DC feedback used in the CSA is similarto the one described in [5].  The average recoverytime of the CSA can be adjusted from 50 ns to 1 msby an external current source without requiring anyreset signals to be transmitted across the sensitiveanalog region.  The output of the second stageconnects to a 2 bit flash ADC and a discriminator.ColumnPixelCellChipLog.EOCLog.EOCLog.EOCLog.Control BusData BusFigure 1. FPIX1 Block diagram.HitAmplifier DiscriminatorADC Bit[1:3]ChargeSensitiveAmplifierVddaThrThr 1,2,3Figure 2. Front-end Block diagram.The discriminator output Hit is asserted when thesignal at the input of the discriminator is higher thanthe threshold (Thr).  The flash ADC consists of threecomparators directly connected to SR flip flops insidethe pixel cell.  The four thresholds (common for allpixel cells) are input to the chip as DC levels.  Duringreadout, tri-state buffers connect the outputs of theADC flip flops to the EOC Logic, where they areencoded into two bits.The digital interface of the pixel cell is depicted inFigure 3. It has two major components; theCommand Interpreter, and the Pixel Token and BusController.  The Command Interpreter has fourinputs, corresponding to the four EOC commandSets.  Commands are presented by the EOC Logicsimultaneously to all pixel cell Interpreters in acolumn.  When an Interpreter is executing the inputcommand and the Hit output from the discriminatoris asserted, the Interpreter associates itself with theparticular EOC Set that is issuing the input command.Simultaneously, it alerts the EOC Logic to thepresence of a hit via the wire-or’ed HFastOR signal.After the association to a particular EOC Set has beenmade, the Interpreter ignores commands from allother EOC Sets.  The pixel hit information is storedin the cell until the associated EOC Set issues anoutput or reset command.When the associated EOC Set issues the outputcommand, the Interpreter issues a bus request andasserts the wire or’ed RfastOR signal.  This operationis executed independent of the master readout clock(Rdclk)1.  The balance of the readout proceedssynchronous with the Rdclk.  The EOC Logicprovides a column token on the bottom of the columnas a means to regulate bus access.  The token quicklyskips pixel cells with no information until it reaches acell that is requesting the bus.  This propagation to ahit pixel is done in less than one clock cycle, even ifthe pixel is the last in the chain.  At the next risingedge of the Rdclk, the hit pixel with the column tokenloads its data onto the bus and drives it to the EOClogic for one clock cycle.  In parallel, the columntoken is transmitted to the next hit pixel, pipeliningthe output of the Pixel Cell with the token passing.This allows the readout of one Pixel Cell per clockcycle, without any wasted Rdclk cycles.  The data iscomposed of the ADC count Bits[3:1] and the rowaddress Radd[7:0].  As the hit pixel is read out, itautomatically resets itself and withdraws its assertionof the RFastOR.  The RFastOR returns to its inactivestate while the last of the hit pixels is being read out.This way, the EOC Logic is able to detect when thelast hit pixel in the column is being output.  At thenext rising edge of the Rdclk, control of the on-chipbus is transferred to the next column with hit data.                                                          1 Rdclk is reffered to as MClk in figure 4.CommandInterpreterHit CTkin CTkoutEOCCommandSetHFastORPixel Token& BusControllerBreq Radd[0:7]MclkRFastORFigure 3. Pixel Cell Digital InterfaceAt any given time, only one EOC Set is permitted tobroadcast the input command.  This insures that hitpixel cells are associated with only one EOC Set.Pixel cells that have not been hit continue to monitorall four EOC Sets, waiting for a coincidence of hitand input commands.2.2 End of Column LogicFigure 4 shows a block diagram of the EOC Logic.It consists of a Priority Encoder and four EOCcommand Sets.  The EOC Sets themselves consist ofa timestamp register, a state machine for generatingthe appropriate EOC commands, and twocomparators.The Priority Encoder selects one EOC Set to issuethe input command. When there is a hit somewherein the column, the HFastOR signal is asserted, andthe state machine inside the assigned EOC Setresponds by latching the Current BCO (CBCO) in itsEOC timestamp register and by issuing the idlecommand at the next rising edge of the BCO clock.This ensures that all pixels in a particular column hitin the same clock period are associated with a singleEOC Set.  The Priority Encoder assigns the next EOCSet to issue the input command to the column (at therising edge of the BCO clock).  Since the EOC Logichas four EOC Sets, pixel cells in the column can behit without loss of data in four different crossingsbefore any data is read out.A “hit” EOC Set waits for matches with its storedtimestamp BCO (SBCO).  If the match is between theRequested BCO (RBCO) and the SBCO, the EOCSet broadcasts the output command, and if the matchis between the Current BCO (CBCO) and the SBCO,it broadcasts the reset command.  Any of the bits inthe comparison between CBCO and SBCO can beprogrammed to be ignored.  This allows for a userdefined reset delay.  This feature is designedprimarily for the externally triggered readout mode.EOCSet 0FastORPriorityEncoderEOCCommandSetMclkEOCSet 1EOCSet 3EOCSet 2CBCORBCOCol. Token& BusControllerETkin ETkoutMClkBClkCTkoutCTkinFigure 4. End Of Column LogicA second state machine is implemented inside theColumn Token and Bus Controller, to control the access tothe EOC data bus.  This access is arbitrated by an EOCtoken.  As soon as there is a match between the RBCO andthe latched CBCO, the Column Controller issues the CTkintoken to the column, and waits for the EOC Token In(ETkin) from the Chip Logic.  When the ETkin is asserted,the Column Controller enables the pixel data onto theinternal data bus, and stays in this state until all hits in thecolumn are read out.  The Column Controller now passesthe EOC token to the next EOC Logic by asserting ETkout.The early delivery of the CTkin to a column, even beforethe ETkin is received, allows for the pixel data to beasserted on the internal data bus as soon as the EOC tokenarrives at the EOC Logic.  This, added with the assertion ofETkout as soon as CTkout is received by the Columncontroller, allows for full clock speed readout of the pixeldata, even when the chip finishes the read out of onecolumn and starts the read out of the next.A more detailed description of the complete readoutincluding the chip logic can be found in [6] and [7].3. RESULTSWe have thoroughly tested the FPIX1 chip both withand without a detector. In this paper we will focus on chipsbump bonded to detectors. We have bonded several chipsto different types of detectors (All from the same wafer formSeiko) that were provided by the ATLAS collaboration.Figure 9 shows a chip-detector assembly on the test PCB.The readout was found to work as expected, despite aminor bug. A typical output sequence of the FPIX1 RO isshown in figure 11 as captured from a logic analyzer. Thedata valid bit (DV) indicates the presence of a valid data,which should be strobed at each negative edge of thereadout clock. First the chip outputs the chip ID and thetime stamp then the addresses and the ADC values of allpixels hit during that time stamp.Figure 10 Bump Map.Figure 8 Noise & Threshold Vs VDET. Figure 7 IV characteristics of an ST1 detector.Figure 6 Noise distribution. Figure 9 Threshold distribution.Figure 5 FPIX1-detector assembly.Figure 11 A typical FPIX1 output sequence (6pixels hit)Figure 7 shows typical DC characteristics of anassembled n-on-n detector in which the individual pixelsare separated by individual floating p-implants (PSTOP).To precisely determine the full depletion voltage we plotthe noise and the threshold (of a given channel at a givenbias setup) versus the detector reverse bias voltage.Figure 8 depicts one such a curve. We have found thatall detectors deplete at around 50V, but have differencesas high as 100V in the breakdown voltages of detectors.An important design criterion is threshold and noisedispersion within one chip. Without a detector, weconsistently measured across several chips thresholddispersion of about 250e-, at low threshold setup. Thenoise averages about 40e- rms. with a standard deviationof less than 3e-.  After bump bonding to a detector thethreshold dispersion was about 300e- rms. and the noisereached about 70e- rms. After bonding the detectors wehad to disable some extremely noisy pixels (about 25 inthe bottom left corner of the detector as shown in figure10) to perform adequate measurements. The excess noiseis believed to be due to some bumps, being shortedtogether and/or to the guard ring.Figure 9 and 6 depicts the threshold and noisedistributions of an FPIX1 bumped to a p-spray detector.Similar results were obtained with the other type ofdetectors.We were unable to detect any cell to cell cross-talk at a2000e- threshold with the maximum input charge of80000e-. The test was done by injecting only one celland looking for any of its neighbors to fires. The test wasperformed at different locations across the chip. Theresult was the same for p-spray and p-stop detectors.Table 1 Summary of the main results.Supply voltage 3.3V (+/- 25%)Analog supply current 18µA/cellNoise (ENC) 70e-Threshold dispersion 280e-Timewalk 50nsDynamic range 40ke-Threshold control 2ke- to infinityToken skip delay 192ps, 5.2GHz skip rateMaximum RO clock 30MHzCell to Cell Xtalk None at 2ke- threshold.4. CONCLUSIONAs summarized in table 1, most of the obtained resultsmeet or exceed the preliminary specifications suggestedby the BTeV collaboration. Our immediate plan is tobeam test the described system and have a confirmationregarding the required resolution in the analoginformation. We are also planning to design a radiationtolerant quasi final chip next year. A small prototypefront-end circuit has been already submitted forfabrication in a 0.25µ CMOS process.5. REFERENCES[1] Artuso, M. and Wang, J., “Some further studieson factors affecting the pixel resolution,” BTeVint. note, July 1998. See also [6].[2] Mekkaoui, M., et al., “Results from the FPIX0chip bump-bonded to the ATLAS pixeldetector,”  Proc. 4th Workshop on Electronics forLHC Experiment, Rome, Sept. 21-25, 1998[3] Wright, J., et al., “A pixel unit-cell targeting16ns…” LBL-32912, Berkeley, 1992.[4] Mekkaoui, A., “FPIX0: A prototype pixel FE chipat Fermilab,” Proc. 3rd Int. Meeting Front EndElect. for High Resol. Tracking Det., Taos, NM,Nov. 1997.[5] Blanquart, L., et al., “Pixel analog cellsprototypes for ATLAS in DMILL technology,”Nucl. Instrum. Meth. A395, pp. 313-317, 1997.[6] Christian, D., et al.,  “ Development of a pixelreadout chip for BTeV”, Nucl. Instrum. Meth.A435, pp. 144-152, 1999.[7] Cancelo, G., et al., “High Readout Speed PixelChip development at Fermilab”  Proc. 4thWorkshop on Electronics for LHC Experiment,Rome, Sept. 21-25, 1998[8] The ATLAS Collaboration, “ATLAS TDR 5,''CERN/LHCC/97-17

FPIX1: An Advanced pixel readout chip

FPIX1: An Advanced pixel readout chip

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