Bisello, D

French, M

Fulcher, J R

Hall, G

Jones, L

Kaminski, A

Paccagnella, A

Raymond, M

Stavitski, I

Wyss, J

CERN Document Server

Single Event Upset Studies on the APV6 Front End Readout ChipJ Fulcher∗, G Hall, M RaymondImperial College, London, UKD Bisello, A Paccagnella, I Stavitski, J Wyss, A KaminskiPadova University, Padova, ItalyM French, L JonesRutherford Appleton Laboratory, Didcot, UK∗ Corresponding author, email jr.fulcher@ic.ac.ukAbstractThe microstrip tracker for the CMS experiment at theLHC will be read out using radiation hard APV chips.During high luminosity running of the LHC the trackerwill be exposed to particle fluxes up to 106 cm-2 s-1. Thishigh rate of particles introduces a concern that the APVcould occasionally suffer from Single Event Upset(SEU). In order to evaluate the expected upset rate theAPV was run under controlled conditions in a heavy ionbeam. The upset cross-sections of the main digital partsof the chip have been measured at two values of incidentLinear Energy Transfer (LET). A theoretical predictionof both threshold LET and cross-section is presentedalong with the experimental measurements.1. INTRODUCTIONThe high radiation environment of the LHC demands thatthe electronics in the central regions of the CMS detectormust be designed to withstand large doses of ionizingradiation. One result of such high rates is to introducesusceptibility to Single Event Effects (SEEs). There aremany different SEEs; the one we are interested in isSingle Event Upset (SEU), which affects the memoryelements of digital circuits.The CMS collaboration has adopted a readout systembased around the APV chip series, a mixed modeamplifier buffer chip with programmable digital controllogic. During the research and design phases of the APVchip, much care has been taken to assure a high degree oftotal dose radiation tolerance. There are two versions ofthe chip; the APV6, fabricated in the Harris AVLSI-RABulk CMOS process [1] and the APVD, fabricated in theDMILL process [2]. Both of these have feature sizes oforder 1.2 microns. Extensive testing has been carried outon representative test structures from various processingruns, and the degree of radiation tolerance of theseprocesses has been thoroughly investigated [3]. However,the susceptibility of the APV to SEU is not well known,nor is there much relevant data for comparable types ofcomplex mixed analogue digital chips. A new version ofthe APV will be fabricated in a 0.25µm technology [4];therefore future tests will perform a full investigation ofthe sensitivity of both processes.With a view to calculating a prediction of the upset rate inthe final system, a first evaluation of the SEU sensitivityof the bulk CMOS process has been carried out byplacing the APV6 in a beam of heavy ions, at the Tandemaccelerator, INFN Legnaro, Italy.1.1 The APV6The APV6 front-end chips consist of 128 channels, eachof which is made up of a pulse amplifier and shaper thatfeeds a 160 deep analogue pipeline capable of storinginput pulses for up to 4 µs. On an external T1 trigger thedata is retrieved from the pipeline and then output, via a128 : 1 multiplexer. The output stream consists of a setof analogue levels retrieved from all 128 channels and adigital header. This header comprises an error flag and aneight-bit address that indicates which one of the 160pipeline locations had been marked for readout by thetrigger pointer. Control of the various chip operationmodes and bias settings is achieved via a standard I2Cserial bus link.The vulnerable parts of the chip are the digital circuits. Inthe APV these comprise the digital pointers of thepipeline, the FIFO address memory, the I2C control logicand data registers and other main control logic. In thefirst evaluation of the SEU vulnerability, upset cross-sections have been measured for the pipeline logic andFIFO combination, and the I2C data registers. Theremaining control logic was masked from the beam.2. THEORY2.1 The SEU phenomenonSEU is a non-destructive phenomenon, which affectsboth dynamic and static memory registers thattemporarily store logic states. It manifests itself as a softerror appearing in a device and is caused by thedeposition of charge by an ionizing particle.Depending on the state of the cell, a sufficient injection ofcharge at points 1 or 2, in Figure 2.1, will cause the stateof the cell to invert.VddNMOSPMOS12Figure 2.1 Schematic representation of a memory cellcomposed of two cross coupled inverters, and its circuitdescription .In the APV soft errors could cause a variety ofundesirable effects, some of which would result intemporary malfunction and possible loss of data. In theevent of such errors the APV can be reset and after alatency ( ~ 3 µs ), normal operation would resume.For an upset to occur two basic criteria must be met. Theincident particle must provide a high enough LET1(Linear Energy Transfer) in order to free electrons andcreate a charge deposit larger than the critical charge Qcrit,which is the minimum charge required to cause the circuitto invert logic state. The particle must also strike closeenough to the sensitive part of the circuit, represented bythe arrow in figure 2.1, so that charge can be collectedfast enough. The sensitive volume of one memoryelement is defined as being that volume in which theincident particle must strike to cause an upset, which canbe approximated by the drain implant volume of the ‘off’NMOS transistor and that of the source of the ‘off’PMOS transistor. The combination of these two volumesmakes the total sensitive volume. In actual fact the truesensitive volume is larger, the reason for which isexplained in section 2.4.2.2 Upset cross-sectionThe cross-section, σ, for SEU’s is defined at normalincidence as:[ ]2cmNeventsΦ=σ [2.2.1]Where Φ is the total incident particle fluence, and Neventsis the number of events (SEU) counted during the test.Figure 2.1 shows a typical cross-section curve. In thecase of heavy ion irradiation these curves typicallyrepresent σ of the device as a function of LET of theincident ions.1 LET is a measure of a particle’s rate of energy transfer in aparticular material and is given byρ1.dxdELET = , where ρ isthe density of that material. All values of LET in this paperrefer to energy transfer in silicon.Figure 2.1 A typical cross-section curve.LETthreshold is the minimum LET for which upsets canoccur and σsat is the saturating cross-section for highvalues of LET. These two defining features of the devicebehavior can then be used to reconstruct the curveanalytically, which enables an interpolated prediction ofthe upset rate for other forms of radiation. In the case ofthe CMS tracker, the required calculations arecomplicated since the incident particles are typically ofsingle charge and therefore only cause large enoughionization by virtue of interactions with silicon latticesites. Monte-Carlo simulations are required and havebeen developed at CERN [5].2.3 Predicting the threshold LETThe critical charge Qcrit is estimated by assuming that, inorder to cause an upset, the voltage at nodes 1 or 2 infigure 2.1 must be changed by at least half of thedifference between logic 0 and logic 1. In the APV logic0 is at –2V and logic 1 is at 2V, which gives us a requiredupset voltage of 2V.The capacitance of these nodes is 30fF (15fF for eachtransistor gate), Qcrit is given by :fCfFVQcrit 60302 =×= [2.3.1]Using 3.6 eV per electron, the critical energy required isgiven by:13506.3 =×=eQE critcrit keV [2.3.2]We can convert this value into a measure of LET, sincethe depth of the sensitive volume is small enough toallow us to approximate to the surface LET of theincident particle. The depth, z, is given by that of theepitaxial layer of the device, which is roughly 2 µm.LETthreshold specific to the APV6 is given by:129.2 −== mgMeVcmzELET critthreshold ρ [2.2.3]This represents a conservative estimate of the expectedthreshold LET.2.4 Predicting the upset cross-sectionThe total number of sensitive nodes in the pipeline logicis 960. The surface area of each node is 12×10-8 cm2.Therefore, the total sensitive cross-sectional area of thepipeline logic is:2610115 cmpipeline −×=σ [2.4.1]For the I2C registers there are 128 sensitive nodes, hence:272 10154 cmCI −×=σ [2.4.2]These values represent the total physical cross-section ofthe sensitive volumes in the circuits. In reality thesaturated cross-section will be larger than this, since highLET particles striking near the edge of the sensitivevolume can create charge clouds.3. TESTING THE APV63.1 PreparationBefore setting up the system in the beam area apreparatory system was set up in the lab at IC. Thesystem reflected all the requirements of the final system,including long cables to run between the beam area andthe barracks, vacuum prepared interface cards and cables.The system was tested fully, making data taking runs as ifin the beam. The data from these control runs werestored to be accessed for comparison at a later date.3.2 HardwareFigure 3.1 Schematic representation of the hardwareThe test beam setup was effectively identical to the APVreadout chain in the lab. Main control was performed by aPC running LabVIEW, which communicated with theVME crate via a PCI VME interface. The triggersequence for the APV was provided by a SEQSIsequencer, and control of the APV performed by a VI2Cslow control interface. The output from the APV wasdigitized by a flash ADC.3.3 SoftwareThe control and data acquisition was carried out bycustom designed software developed in LabVIEW. Themain tasks were to provide resets and triggers, via theSEQSI, to capture the digitised APV output data frame,via the ADC, to perform rudimentary on-line analysis andto save data to disk. The on-line counting of events wasnecessary for fine-tuning of the sensitive time in order toensure that event counting was non-saturated (see section3.6). Other on-line information included an overall countof upsets and a total sensitive elapsed time counter. Thesoftware also included I2C control for testing the APVstatic registers.3.4 Masking APV sectionsOne of the requirements of the system was the ability tomask off sections of the APV. The masks were madefrom copper plates approximately 1mm thick, to providean adjustable aperture. This enabled us to select the partsof the chip to test. It was also possible to reduce the upsetrate by reducing the exposed area of these parts.3.5 Seeing upsetsOne part of the chip where it was possible to detectupsets, and probably the most useful to test, is thecombination of the pipeline logic and FIFO. In the eventof an upset there are two possible outcomes: either theerror bit in the output data frame is set, or the pipelineaddress in the output data frame is corrupt. The mostlikely cause of a corrupted address is an upset changingthe pipeline column address stored in the FIFO. Theerror bit is set if an upset in the pointer logic causes thelatency of the trigger pointer to change. Only a smallproportion of upsets produce both outcomessimultaneously.Figure 3.2 Location of tested circuits.One can also test for events in the I2C registers bywriting defined values, reading out the values after a setperiod of time, and comparing them with initial values.In this case it is possible to detect the individual cellswhich have been upset.When measuring upsets in such a chip one has to becareful that upsets do not interfere with chip operation.This can be achieved by exposing only the parts of thechip shown in figure 3.2, masking off the vital controllogic and running the chip for short time periods, toensure only a small number of upsets during each. It isimportant that the average number of upsets per timeinterval is less than one (see section 3.6). The runningtime per measurement, when the chip is sensitive toupsets, is defined as the sensitive time (ST). Whenmeasuring the upset rate, following each ST there is areadout period, this is repeated many times to make aPipelineI2Cgood measurement. For the pipeline a typical runconsists of 100,000 STs, and for the I2C, 100.Figure 3.3 shows the definition of Tsensitive the totalsensitive time for one run for the pipeline logic.ST STReset Trigger Reset TriggerReadout periodFigure 3.3 definition of ST for the pipeline logic3.6 Non-saturated measurements of events inthe pipeline logicOne important issue is undercounting of events in thepipeline logic. Only one error can be detected withineach sensitive time interval, as more than one error stillonly produce symptoms consistent with one error. If welose events by undercounting then the measured upsetrates begin to saturate, hence one must ensure that thenumber of events is less than half the number of sensitivetime intervals. In order to achieve this condition one canadjust the length of the sensitive time interval, adjust theupset rate by changing the beam flux (this method iscrude and unreliable) or use masking to change theexposed area of the chip.3.7 The TANDEM Van der Graaf acceleratorThe TANDEM is located at the INFN laboratory inLegnaro. Table 3.1 shows the ions that were available forthis test and their corresponding LET in silicon.The TANDEM is capable of producing many more ionspecies, those in table 3.1 being chosen specifically forthis test to cover a useful range of LET values.Ion Li C O F Si Ni AgLET(MeV.cm2.mg-1) 0.38 1.5 2.9 3.8 8.7 28.7 54.9Energy (MeV) 55 92 106 116 153 214 259Table 3.1 Available ions for APV6 testThe typical beam flux was in the range 1x104–1x107 cm-2s-1. For each ion this value was set to a constant. Due toproblems during the experiment there was only enoughtime to test the APV6 under two ion beams: Oxygen,which had a typical flux of 2x106 cm-2 s-1 and Silicon,which had a flux of 2x105 cm-2 s-1. The chip was mountedinside a vacuum chamber, which was held at a pressure of10-6 mbar.4 RESULTS AND CONCLUSIONSMeasurements were made for the SEU cross-section ofboth the pipeline and I2C logic at two values of LETusing Oxygen and Silicon ions. For Oxygen a largenumber of readings with high fluence were made and noupsets were observed. Thus it can be deduced that thethreshold for both pipeline and I2C logic is above 2.9MeV.cm2.mg-1. Silicon, on the other hand, produced asignificant upset rate, giving the following results.4.1 Error distributionIn order to be confident that events observed were causedby the ion beam, the distribution of these events with timewas measured. For random processes the distributionshould be described by Poisson statistics.80604020086420Run = P324Entries = 200Average = 0.76Rms = 1.37026time bin = 0.11125 sCalculated PoissonFigure 4.1 SEU distribution for pipeline logicFigure 4.1 shows a typical distribution of 200 SEUsobserved in the pipeline logic. All data showed a good fitwith Poisson statistics.4.2 Pipeline cross-sectionThese data represent errors in the pipeline logic only,which are identified as having caused the error bit to beset in the APV6 data header. All of the results that followwere made with a ratio of SEUs to number of sensitivetime intervals ~ 1/1000. Under these conditions onewould expect the upset cross-section to show nodependence on the sensitive time.100x10-6806040200UpsetCross-section[cm2 ]200x10-615010050Sensitive Time [s]APV6 Pipeline LogicSi IonsLET = 8.5 MeV.cm2.mg-1σave = 4.41 x 10-5cm2Figure 4.2 Variation of cross-section with sensitive timeFigure 4.2 confirms this expectation within an acceptablestatistical variation, with the average cross-section of (4.4± 0.2) x 10-5 cm2.Tsensitive = Ntriggers . STNumber of errors per binFrequency80x10-66040200UpsetCross-section[cm2 ]14012010080604020LatencyAPV6 Pipeline LogicSi IonsLET = 8.5 MeV.cm2.mg-1σave = 3.71 x 10-5cm2Figure 4.3 Variation of cross-section with latencyA similar test was made by varying the latency of thetrigger pointer. Again one would expect to see novariation in the cross-section, and figure 4.3 shows thatthe measured value varies very little, with an average of(3.7 ± 0.1) x 10-5 cm2.If one assumes the cross-section to be constant at onevalue of LET, the average of all measurements for thecross-section of the pipeline logic can be taken as a firstestimate, this gives (4.1 ± 0.1) x 10-5 cm2.4.3 I2C registers cross-sectionSimilar measurements made for the upset cross-section inthe I2C registers again show consistent results withvariation in the sensitive time. Figure 4.4 shows theaverage cross-section to be about (1.5 ± 0.9) x 10-5 cm2.40x10-63020100UpsetCross-section[cm2 ]0.50.40.30.20.1Sensitive Time [s]APV6 I2C RegistersSi IonsLET = 8.5 Mev.cm2.mg-1save= 1.56 x 10-5cm2Figure 4.4 Variation of cross-section with sensitive time4.4 Discussion and future measurementsWith only two measurements of cross-section it isimpossible to draw a curve of cross-section against LET.Figure 4.5 shows a possible range in which the curvecould lie, illustrating the uncertainties that still remain.It is clear that more points are needed in order to make anaccurate measurement of the saturated cross-section, andthe threshold LET. From figure 4.5 the threshold liesbetween 2.9 and 8.5 MeV cm2 mg-1.10 - 810 - 710 - 610 - 510 - 410 - 30?Si (LET=8.5)LET MeV cm  mg2 -1O (LET=2.9)Cross-section MeV cm-210 20 30Figure 4.5 Possible range for the cross-section curveTable 4.1 shows a comparison between the predictions insection 2 and the measurements above.Prediction MeasuredThreshold LET(MeV.cm2.mg-1) 2.9 2.9 – 8.5Cross-sectionI2C (cm2) 1.5 x 10-5 1.5 ± 0.9x 10-5Cross-sectionPipeline (cm2) 1.2 x 10-5 4.1 ± 0.1 x 10-5Table 4.1Tests to complete the measurements are planned for laterthis year. This will then enable extrapolation to CMS tobe made and a prediction for the expected upset rate inthe tracker. We also intend to test the APV25S0, the newversion of the chip fabricated in a 0.25 micron process.6. ACKNOWLEDGEMENTSWe thank PPARC for financial support, the INFN and allthe technicians at the TANDEM for the time in the beamand technical support at Imperial College and Universityof Padova.7. REFERENCES[1] M.Raymond et al, “The APV6 readout chip for CMSmicrostrip detectors”, Third workshop on electronics forLHC experiments, 21 Oct 1997, p.158[2] R. Turchetta et al, “APVD: a CMOS mixed analogue-digital ciruit for the silicon tracker in CMS”, ThirdWorkshop on Electronics for LHC Experiments, 21 Oct1997, p.163[3] M.Raymond et al, “Radiation Tolerance Studies ofHarris Test Structures”, Fourth workshop on electronicsfor LHC experiments, 21 Sept 1998.[4] L.Jones et al, “The APV25 Deep Sub Micron ReadoutChip for CMS Microstrip Detectors”, These Preceedings.[5] F. Faccio, M. Huhtinen, “First evaluation of thesingle event upset (SEU) risk for electronics in the CMSexperiment”, CMS Note1998/054

Single event upset studies on the APV6 front end readout chip

Single event upset studies on the APV6 front end readout chip

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