Colas, Jacques

Colas, J.

HAL-IN2P3

Overview of the ATLAS-LARG electronics

HAL Université de Savoie

Hal - Université Grenoble Alpes

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OVERVIEW OF THE ATLAS LARG ELECTRONICSJ.Colas (LAPP, Annecy-le-Vieux, France) for the ATLAS-LARG collaborationAbstractThis document briefly reviews the main detectorcharacteristics relevant to the read-out electronics of theATLAS Liquid Argon calorimeters, lists the mainrequirements and discusses briefly the general architectureand the basic building blocks. The next steps in theconstruction of the ATLAS electronics are outlined.1.  INTRODUCTIONThe Liquid Argon sampling calorimeter technique isused for all electromagnetic calorimetry covering thepseudorapidity interval |η| < 3.2 and also for hadroniccalorimetry from |η| = 1.4 to the acceptance limit |η| =4.8. The global layout is shown in Figure 1. The centralcryostat contains the barrel electromagnetic calorimeter(EMB). Each end-cap cryostat houses an electromagneticcalorimeter (EMEC), two hadronic wheels (HEC) and oneforward calorimeter (FCAL). Close to ~190 k highprecision, high dynamic range and low noise electronicchannels are needed to read out this detectorFigure 1: 3D view showing the Liquid Argon calorimetersystem and the location of the front-end electronicsCommon electronics is used everywhere, with theexception of the very front-end where the HEC uses coldpreamplifiers. This minimizes design effort, standardizeshardware and will facilitate maintenance.A great deal of work has been done to define thiselectronics system and to prototype it. Samples of nearlyevery front-end board have been built for a total of about6000 read-out channels. They are now being installed inthe test beam at CERN. This electronics is being used totest and qualify ATLAS calorimeter modules. Thisprovides a very valuable experience with the system.This note briefly reviews the main detectorcharacteristics relevant to the read-out electronics, lists themain requirements and discusses briefly the generalarchitecture and the basic building blocks. The next stepsin the construction of the ATLAS electronics are outlined.More detailed information can be found in [1, 2].2.  DETECTOR CHARACTERISTICSThe calorimeters are finely segmented bothlongitudinally and transversally for a total of ~190 kactive read-out channels. These channels are groupedconsistently to form ~ 5120 trigger towers (see figure 2).Figure 2: Typically 60 cells are summed to form pointingtrigger towers with a size ∆η  ×  ∆φ = 0.1 × 0.1.As sketched on Figure 3 the detectors deliver on theirelectrodes a triangular-shaped current signal with a fastrise time (a few ns) decreasing to zero at the end of thedrift time of ionization electrons in liquid argon (~ 450ns). For the FCAL, since the argon gap is smaller, thepulse duration is shorter (~ 50 ns).Figure 3: Signal shape as produced in the detector(triangle), and after shaping (curve with dots). The dotsrepresent the position of successive bunch crossings.Calorimeters CalorimetersCalorimetersHadronic Tile EM AccordionForward LArCalorimetersHadronic LAr End CapFront-EndElectronics2x134x1 PresamplerStrip layer4x4 Middle layer2x4 Back layerPointing trigger tower ∆η x ∆φ = .1x.1The amplitude of the current varies from one sub-detector to another. A value of 2.8 µA/GeV is typical forthe EM accordion calorimeters; this drops down to ~0.3µA/GeV for the HEC. This signal is delivered on thedetector impedance, which, to a very good approximation,is a pure capacitance from as low as 75 pF to as high as 2nF. More information can be found in the LARG TDRSection 10.2. [2]3.  REQUIREMENTSThe main requirements for the read-out electronics canbe summarized as:• The dynamic range of the input is at least 16 bits. Thedegradation introduced by the read-out system shouldbe minimal.• The read-out system should be inter-calibrated to betterthan 0.25% over the whole energy range, in order toachieve a small constant term in the energy resolution.• The amount of coherent noise per cell should be lessthan 5% of the level of incoherent noise.• A pipeline with a depth of at least 2.5 µs should beprovided; in addition a large enough derandomizingbuffer and a fast enough read-out should allow for amaximum Level-1 trigger rate of up to 75 kHz.• Cells should be summed in trigger towers∆η  ×  ∆φ = 0.1 × 0.1 and the result sent out to theLevel-1 processor. The required precision for the analogtrigger sums is 5%.• A fair fraction of this electronics will be located in anarea with limited access. High reliability is thus aconcern. In addition, although radiation levels at thatlocation are not very large (1012 n/cm2/yr; 20 Gy/yr; 1010ionizing particles/cm2/yr), this electronics has to beradiation tolerant.• The large number of channels (~ 190 000) involvedrequires development of a system with low powerconsumption and moderate cost.4.  READ-OUT ARCHITECTURESignals from the detectors are processed by variousstages before being delivered to the DAQ system.Figure 4 shows the read-out architecture as well as thebasic elements of the system: preamplifiers, shapers,pipeline memory, digitization, and digital filtering. Thedata are then sent off to the Level-2 buffers. Much of thedigital electronics: control, digital filtering, and Level-2buffering, is located off the detector, in a control room.This limits digital activity close to sensitive analogelectronics to the absolute minimum. The off-detectorelectronics will use standard non radiation-hardtechniques. It will be easily accessible, and can bedelivered relatively late; the latest available technologycan be used. It will also be more easily upgradable.Layer SumShapersCalibrationDACLcRcClockIPreamplifiers ΣBuffering      &    ADCCalorimeterMonitoringOptical LinkT=90KCdFront End  Board Tower  Builder ControlRODSystem ControlCPULEVEL 1PROCESSORLEVEL 1INTERFACECTPTTCTrigger CavernExternal Triggers40MHz CLKLV1 Acc.ControlReset32 Bits40 MHz~180k~15kNetworkDAQΣTTC InterfaceCryostatOn DetectorReadout Crate (60)Front End Crate (60)MotherboardControllerSCA  (144 Cells)Figure 4: Block diagram of the read-out electronics. Inthe drawing warm preamplifiers are located on the front-end board, which is the case for the EM and FCALcalorimeters. For the hadronic end-cap calorimeter, apreshaper - that interfaces preamplifiers located in theliquid argon to the standard shaper chip - replaces them.The clock and control signals (level1 accept, resets...)are generated in the trigger room, where special care hasto be taken to minimize trigger latency, and fan-out to thevarious boards using the TTC system developed by theRD12 collaboration. The global system is split into 8partitions, which can run independently if needed.The sensitive analog electronics is housed ’on-detector’,in a front-end crate attached to the cold to warmfeedthroughs, in the crack between the barrel and end-capcalorimeters and at the rear of the end-caps (see figure 1).This crate is positioned on top of the warm feedthroughflange, effectively becoming an extension of the cryostatFaraday cage. This should efficiently shield the LARGread-out electronics against external electromagneticradiation. In addition, this keeps the warm part of thesignal and calibration cables to a minimum length andtherefore minimizes the associated attenuation and noise.The design of the crate system is now well advanced asexplained in [3]. It strives to minimize pick-up noise thatmight be coherent over many channels. It also providesfor an efficient water cooling of the ~3kW dissipatedpower. Crate production will start early 2000.5.  THE FRONT-END SYSTEMIn the cold, a system of G10 boards gangs electrodestogether to form readout cells and holds precision resistorsthat inject calibration pulses. Small diameter coaxialcables connect to these boards and bring signals to thecold to warm feedthroughs. All these parts are already inproduction [4, 5].The front-end crate (FEC) contains several types ofboards.The calibration board houses 128 precision pulsers whichinject precisely known current pulses, covering the wholedynamic range, as close as possible to the read-outelectrodes through high-precision resistors located in thecold, to simulate energy deposits in the calorimeters. Thetiming of the calibration pulses is set to reproduce thetiming of physics signals, taking into account the variationof time of flight. More information can be found in the G.Perrot’s contribution to these proceedings and in [6].Front-end boards (FEBs) [7] also house 128 channels:•  They amplify and shape the input analog signals. Threegains are used to cover the full dynamic range [8].• They sum calorimeter cells by trigger tower within eachdepth layer, and drive the summed signals to the towerbuilder board.• They store the signals in a 144 cell deep analog memory(SCA) waiting for the decision by the first level oftriggering,• They digitize the selected pulses, and transmit onoptical fibres the multiplexed digital results.Figure 5: Photograph of a FEB board. The input signalscome into the board from the two external connectors at thebottom. The shaped and summed signals for the triggerare output on the middle connector at the bottom. Thevarious sections: preamps, shapers, SCA’s, ADC’s areclearly visible. Voltage regulators are laid out in the toprow.Production of amplifiers is now well-advanced [9] ascan be seen from H. Brettel’s and M. Citterio’scontributions, and a preproduction run is going to beordered very soon for shapers and SCAs.For the EM barrel and endcap calorimeters, TowerBuilder Boards (TBBs) [10] are used to perform the finallevel of analog summation to form trigger tower signalsand to transmit the analog signals to the Level-1 cavernfor digitization and processing by the Level-1 triggerprocessor. A prototype has been built and tested in the testbeam. For the HEC and FCAL calorimeter, TowerDrivers (TDB) transmit the signals to the level 1 cavern.Control boards receive and distribute the 40 MHzclock, the level-1 trigger accept signal, as well as otherfast synchronous signals and information to configure andcontrol the various boards in the crate.Monitoring boards read out various monitors, likeliquid purity and temperature sensors.More information about the content of every crate inthe system and on how every calorimeter cell gets routedto its FEB can be found in [11].Quite a substantial amount of power (~ 250 kW) isneeded to supply the large number of electronics channelsin the front-end system. None of this power should betransferred to the surrounding detectors and liquid coolingis mandatory. To minimize the risk for leaks, the coolingfluid will be circulated below atmospheric pressure,typically 600 mb into heat exchanger plates mounted onevery front-end board. Heat conductive pads will be usedto eliminate air gaps between components and coolingplates and maximize heat transfer. Much moreinformation can be found in the contribution by H. Takaiand in [3].The distribution of this large amount of power has to bedone carefully. Each front-end crate will have its own lowvoltage power supplies. Compact high power DC-DCconverters with good noise properties have beenidentified. First tests seem to indicate sufficient radiationtolerance. The current base line is then to locate thesesupplies on top of each crate, minimizing the length of thelow voltage lines and associated loss of power. As this is apoorly accessible area, redundancy is to be built into thesystem. See contribution by M. Citterio for more on this.These supplies will be 'isolated'. Strict control of groundloops will be observed, and there will be only one locationallowed where connection to ground is made. Thecryostats with all their cryogenic lines and services will beelectrically insulated [12].6.  “MODULE 0” ELECTRONICSTo test, in beam, calorimeter modules and to qualifytheir production, a read-out electronics was needed. Thiswas used as an opportunity to prototype the front-endATLAS electronics. About 6000 channels of ATLAS likeelectronics have been produced and ~2000 are alreadyinstalled in the beam. In this exercise, we learnt a lotabout the real ATLAS electronics and some preliminaryresults look already quite encouraging:• The boards were efficiently cooled; the boardtemperatures were between 25 °C and 28 °C (i.e. belowambient at the time of the test) and very stable withtime.• The pedestal stability is very good: 0.1 ADC countsover a 3-week period.• The incoherent electronics noise closely matchesexpected values i.e. ~20/50/35 MeV for the EMfront/middle/back cells.• The coherent noise is slightly larger (5-7%) than theATLAS goal of 5%. However this is already a verygood result as in the test beam we are not yet usingoptical links.• The measured integral non-linearity is below 0.25% onall three shaper gains.• Figure 6 shows samples measured on a single 100 GeVelectron pulse in a middle layer cell. The pulse shape isnice and follows expectation.Figure 6: Samples, 25 ns apart, measured on a single 100GeV electron pulse in a middle layer cell.7.  OFF-DETECTOR ELECTRONICSFor reasons connected with the construction schedule ofthe experiment, the front-end electronics has receivedconsiderably more attention than the electronics that willreside off the detector.7.1  Trigger clock and control systemIn the Level-1 cavern, ~50 meters away from thedetector, signals from trigger towers are received anddelivered to the calorimeter Level-1 trigger processor. Thecentral trigger processor (CTP) will deliver not onlyphysics triggers but also calibration signals and triggers.These signals, together with the 40 MHz clock and othersynchronous commands, are transported to the front-endcrates and to the read-out crates by the TTC system(timing trigger and control) developed in the RD12project. To benefit from the excellent intrinsic timeresolution of the detector (50 ps at high energy), clockjitter should be kept as low as possible (< 100 ps).To ease the timing in of the system, fibers distributingthe clock will be cut to length and/or their transit timemeasured and programmable delay lines in calibrationboards will be preset to reproduce the timing of physicssignals. This should allow not only to align in time thevarious calorimeters, barrel, end-cap... but also to time inthe level 1 processor, the CTP and the distribution of thelevel 1 accept signals. These adjustments will be checkedand refined by analyzing real shower pulses fromcollisions.7.2  Read-out driver systemTo each front-end crate is associated a read-out drivercrate. A set of such front-end crate - read-out driver cratepairs, together with a TTC driver form a partitioncontrolled by a master CPU. Eight such partitions areconsidered 4 for each end of the experiments. This wouldallow running independently the EMB, the EMEC, theHEC and FCAL calorimeters.The read-out driver crate contains:• a CPU connected to the network to control this crateand the associated front-end crate;• a SPAC master module to configure or down-loadparameters into the various boards of the front-end crateor to read back registers [13];• a TTC and BUSY module to receive the TTCinformation, fan it out to the RODs and collect theirBUSY signals• Read Out Driver (ROD) modules, which receive rawdata from the FEBs and produce the correspondingenergy, time, and some form of data quality measure,sending the result to the DAQ, i.e. to the Read OutBuffer (ROB) modules.Fast unidirectional, 1 Gbit/s optical links connect theFEBs to the RODs. A frame of typically five samplescentered on the bunch crossing of interest is sent down thelink to the ROD module for digital processing. This isaccomplished using the well-established method ofoptimal filtering. In practice one obtains a weight for eachsample which results in the minimum error on the energysubject to the constraint that the pulse can be moved intime without affecting the result to first order. Any loss inenergy resolution due to small phase jitter between thepulse and the clock is minimized. The weights are chosento minimize the total noise (electronics pile-up) for thecurrent value of the luminosity, and the quality of thewaveform can be checked to detect events subject to largeADC versus sample #25 ns per sample100 GeV electronMiddle layer cellout-of-time signal overlaps. The available computingpower in these modules will also be used to monitor everychannel. Examples include checking for drift in the phaseof the clock with respect to the particle signal,histogramming energy spectra, and the preprocessing andhistogramming of data during calibration runs. Moredetailed information can be found in the contribution byW. Cleland.8.  NEXT STEPSA major milestone in the development of the LARGelectronics has been met with the production andsuccessful running in of ~ 6000 channels of ATLAS likeelectronics. However, several short cuts had to be takengiven the rather tight schedule:• Digital optical links to connect the FEBs to the RODs:We are currently using shielded twisted copper pairs.These will be replaced by optical links. We alreadyhave hints that this will reduce the amount of coherentnoise. A lot of work has been done to assesscommercial solutions i.e. based on the HP G-Link chipset. The main pending issue there is radiation toleranceand more specifically SEE effects. A lot of informationcan be found in R. Stroynowski’s contribution.• Distribution of TTC signals : In ATLAS, we areplanning to use the standard TTC system as developedby the RD12 collaboration. We plan to test thisdistribution scheme in the test beam set-up as soon asenough standard TTCRx chips become available.• Radiation tolerant electronics : Though the radiationtolerance of our main critical components (preamps,shapers, SCA,...) is now well established, there aremany other areas where a lot of work is needed:a. Power regulators, (we are planning to use the workof P. Jarron et al. from RD49)b. Logic: we are working on moving logic cicuitsdescribed in high level languages (i.e. VHDL) andprototyped in FPGAs to custom ASICs using theDMILL technology.c. ...All this effort aims at producing two full crates ofhopefully final front-end electronics by mid 2001. Thiswould allow exercising these crates for some time beforelaunching the board production for ATLAS by mid 2002.Note however, that some parts of the front-end electronicswill be needed even sooner – i.e. the front-end crates orthe front-end chips: shapers, SCA - or are already inproduction like preamplifiers.9.  REFERENCESMost of the references below are accessible from theWeb, using the EDMS system, starting from the ATLASmain page.1 Overview of the LARG electronics:ATL-AL-EN-00032 ATLAS Liquid Argon Calorimeter TDR:CERN/LHCC/96-413 Liquid Argon Front-End Crate:ATL-AL-EN-00044 The LAR Mother Board System. Documentation:http://www.usatlas.bnl.gov/lar/mb/5 PRR of LArg Cold Cables – Report:ATC-RA-ER-00036 The LARG Calorimeter Calibration Board:ATL-AL-EN-0005ATL-AL-EN-00067 Design of the ATLAS LAr Front End Board:ATL-AL-EN-00098 The LAr Tri-Gain Shaper:ATL-LAR-98-0929 Report on the HEC Cold Electronics PRR:ATL-TC-ER-0013Liquid Argon Calorimeter Preamplifiers PRR:ATL-TC-ER-00xx10 The Level 1 Trigger and the Tower Builder Board:ATL-AL-EN-0007The ATLAS Receiver/Monitor System:ATL-AL-EN-001011 Cabling of the EM calorimeters:ATL-AL-ES-0004ATL-AL-PITT-ES-9.012 Guidelines for Grounding. V. Radeka:http://www.usatlas.bnl.gov/lar/ground.html13 SPAC : Serial Protocol for the ATLAS Calorimeter:ATL-LAR-98-093

Overview of the ATLAS LARG Electronics

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