Dasu, S

Jaworski, M

Lackey, J R

Smith, W H

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CMS CALORIMETER REGIONAL TRIGGER PROTOTYPESS. Dasu, M. Jaworski, J. Lackey, W.H.SmithDepartment of Physics, University of Wisconsin, Madison, WI 53706AbstractThe CMS calorimeter regional trigger system isdesigned to detect signatures of isolated and non-isolatedelectrons/photons, jets, missing and total transverseenergy in a deadtimeless pipelined architecture. Thissystem is comprised of nineteen crates of custom-builtelectronics. Prototype backplane, boards and ASICs builtto validate this design are described here.1. INTRODUCTIONThe CMS detector for the Large Hadron Collider (LHC)presents an extraordinary challenge for its trigger and dataacquisition system. Its trigger system must carefully siftthe 40 MHz data to retain only interesting physics signalsat 100 Hz level while discarding the well-known QCDbackground. The CMS solution to this problem isimplemented in two physical levels, one based on customelectronics and the other relying upon commercialprocessors. The level-1 system uses only coarselysegmented data from calorimeter and muon detectors,while holding all the high resolution data in pipelinememories in the front-end electronics, to produce a triggerdecision in 3 ms. Level-1 triggered events at 100 kHz rateare sifted further in higher levels of triggers implementedas software filters.The CMS level 1 trigger decision is based in part uponlocal information from the level 1 calorimeter triggerabout the presence of physics objects such as photons,electrons, and jets, as well as global sums of Et andmissing Et (to find neutrinos).  Each of these physics isrequired to pass a series of pt or Et thresholds, which areused in making the Level 1 Trigger Decision.The electron/photon trigger is based on the recognitionof a large and isolated energy deposit in theelectromagnetic calorimeter by asking for a small hadronicenergy deposit in the HCAL in the cluster region.   Thereare different thresholds for inclusive electrons/photons,dileptons, and for very high Et electrons. The isolationcuts are relaxed and finally eliminated for triggers withincreasing Et thresholds.2. DESIGN OVERVIEWThe calorimeter level 1 trigger system receives digitaltrigger sums from the front-end electronics system, whichtransmits energy on an eight bit compressed scale.  Thedata for two HCAL or ECAL trigger towers, for the samecrossing, will be sent on a single link in eight bits apieceaccompanied by five bits of error detection code and a‘fine-grain” bit characterizing the energies summed intothe trigger towers (i.e. isolated energy for ECAL, quietfirst longitudinal compartment for HCAL).The calorimeter regional crate system uses 19calorimeter processor crates covering the full detector.Eighteen crates are dedicated to the barrel and two endcaps.These crates are cover the region |η|<3.  The remainingcrate covers both Very Forward Calorimeters that extendmissing ET coverage to |η|<5.Each calorimeter regional crate transmits to thecalorimeter global trigger processor its sum Et , Ex andEy. It also sends its 4 highest-ranked isolated and non-isolated electrons, and 4 highest energy jets along withinformation about their location. The global calorimetertrigger then sums the energies and sorts the electrons andjets and forwards the top four calorimeter-wide electronsand jets, as well as the total calorimeter missing and sumEt  to the CMS global trigger.The regional calorimeter trigger crate has a height of 9Uand a depth approximately of 700mm[1]. The front sectionof the crate is designed to accommodate 280mm deepcards, leaving the major portion of the volume for 400mmdeep rear mounted cards.The majority of cards in the Calorimeter Level 1Regional Processor Crates, encompassing three customboard designs, are dedicated to receiving and processingdata from the calorimeter.  There are seven rear mountedReceiver cards, seven front mounted Electron Isolationcards, and one front mounted Jet Summary card for a totalof 15 processor cards per crate. These cards and anadditional clock and control card are plugged into custom“backplane” which provides point-to-point links betweenthe cards. VME bus is also provided to these cards usinghigh density connectors in top 3U section of thebackplane. In addition there are two slots with standardVME backplane connectors for crate processor andmonitoring cards.2.1 Receiver CardThe Receiver card is the largest board in the crate.  It is9U by 400mm. The rear side of the card receives thecalorimeter data on serial copper cables, and converts fromserial to parallel format. The front side of the card containscircuitry to synchronize the incoming data with the localclock, and check for data transmission errors.  There arealso lookup tables and adder blocks on the front. The                                                [1] J. Lackey et al., CMS Calorimeter  Level 1 TriggerConceptual Design,  CMS TN/94-284 (1994), and an updatein CMS NOTE-1998/074.lookup tables translate the incoming information totransverse energy on several scales.  They are also used totest for Quiet and Minimum Ionization thresholds for eachtrigger tower. The energy summation tree begins on thesecards in order to reduce the amount of data forwarded onthe backplane to the Jet Summary card.  Separate cableconnectors and buffering are also provided for inter-cratesharing.Each card is designed to receive 32 high speed copperlinks from the calorimeter readout electronics. Each linktransmits either two towers of hadronic or electromagneticinformation per crossing for a total of 64 channels from32 ECAL and 32 HCAL towers per card. The presentdesign for the data uses a 24-bit frame including 18 bits ofdata and 5 bits of error detection code. The data consists of8 bits of energy on a compressed scale and one bit of fine-grain information per tower. The error code is sufficient todetect all single and double bit errors as well as manymultiple bit errors. The error bits are necessary for errorlogging and to zero problem channels. The 24-bit worduses 8/10 bit encoding, which implies a 1.2 GHz seriallink. The cable length to the calorimeter electronics isestimated at 20 m.The rear side of the Receiver card has serial receiversbased on the specifications of the Vitesse 7214 4-channelInterconnect Chip. The design provides forcable/connector equalization and the option of transformerisolation on daughter cards.The front side of the Receiver card contains thesynchronization circuitry followed by the memory look uptables, adder tree and backplane drivers. The outputs of thereceivers are not only unsynchronized with the local clockbut are also not necessarily aligned to the same bunchcrossing. The phase alignment circuitry is contained on anASIC (Phase ASIC).  The Phase ASIC deskews the data,decodes the error detection codes and multiplexes theoutput at 160 MHz. The Phase ASIC also provides testvectors for board and system diagnostics.In order to achieve maximum utilization of board space,all the logic following and including the Phase ASIC isrun at 160 MHz. There are also four Error DetectionCodes (EDCs) associated with the four input channels ofeach Phase ASIC. After synchronization, each EDC ischecked against the data.  If an error is detected a single bitis set, one for each incoming channel, and appended to theoriginal EDC code.Lookup tables are required to translate the informationcoming from the calorimeter readout electronics, incompressed format, onto the several different scales usedby the energy adder tree and the Electron Isolation logic.The Hadronic and Electromagnetic energies areindividually translated into eight bits of linear ET with aresolution of approximately 1 GeV.  These values aresummed to provide total energy in 4 x 4 trigger towerregions of the calorimeter. The summation is performedby an Adder ASIC. Thirty-two towers, in a 4 x 8 array,are processed on each card. The transverse energy for eachof the two 4 x 4 trigger tower regions is independentlysummed and forwarded to the Jet Summary card. Thesetwo 13 bit numbers will be multiplexed onto a single setof 13 differential pairs at 160 MHz.The electron/photon finding algorithm itself isimplemented in a separate card. The data required for thisalgorithm is transferred between the Receiver cards and theElectron Isolation cards at 160 MHz.  In order to retainpoint to point transmission data must be transmittedthrough separate drivers on separate backplane lines. EveryReceiver card shares its data with at most 6 ElectronIsolation cards within the same crate.  In addition eachReceiver card sends some of its data off crate at 40 MHz totwo or three neighboring crates.  Crate to cratecommunication is handled by special cables runningbetween the Receiver cards.  This distributes the inter-cratebuffering among the eight Receiver cards in a crate ratherthan attempting to put it all on one or two special cards atthe ends of each crate.2.2 Crate BackplaneThe crate backplane is completely custom with a full9U height.  The top 3U is reserved for a 32 bit VMEinterface.  The remaining 6U is used for the high speeddata paths between individual cards.  All signals in thetrigger data portion of the backplane will be transmittedon point to point links at 160 MHz.  This data rate waschosen because it offers the opportunity to compress thenumber of data lines on the backplane and in the pipelineddata logic by a factor of four.The front and rear insertion of cards in the dataprocessing section of the crate was chosen to allow greaterseparation between cards and to provide a more protectedenvironment for the links connected to the rear mountedReceiver cards.  The increased separation will promotebetter cooling of the cards, and will enable a widerselection of front panel components.2.3 Electron Identification CardElectron Identification algorithm within each 4x8trigger tower region is performed on a smaller 240mmdeep card. Data for thirty-two central towers and twenty-eight neighboring towers is required to determine isolationfor towers on the edge of the 4 x 8 region.  This cardreceives linearized transverse energy on 7-bit scale forECAL and 4-bit scale for HCAL and ECAL fine-grain bitfrom corresponding receiver card. It also receives neighbortower data from up to three other receiver cards in thecrate. Neighbor crate data is transferred through thereceiver cards where it undergoes any realignment ofphase. The algorithm which finds isolated and non-isolatedelectron/photon candidates is implemented in an ASIC.Candidate with highest ET of both types in each of thetwo 4x4 regions covered by the card are transmitted to theJet/Summary card.2.4 Jet/Summary CardJet/Summary card receives 4x4 trigger tower energysums from all Receiver cards in the crate and isolated andnon-isolated electron/photon candidate energies from allElectron Identification cards in the crate. It sorts thesecandidates and forwards top 4 jets, isolated and non-isolated electron/photon candidates to the globalcalorimeter trigger crates on copper cables. In addition italso contains lookup tables to convert the 4x4 ET to Exand EY and adder trees to sum up crate wide sums of allthree of these quantities.3. PROTOTYPES3.1 Work AccomplishedThe goals of prototype development for this triggersystem are many fold. Our strategy was to build as far aspossible full-scale prototypes so that system issues areconfronted up front. Pictures of rear and front views of theprototype crate holding prototype backplane and cards areshown in Figures 1 and 2.Figure 1: Rear view of prototype CMS calorimeterregional trigger crate showing the custom backplane and areceiver card.To prove that high speed and high signal density can behandled, we have built a full sized backplane with point-to-point 160 MHz links and VME control. The backplaneis a monolithic printed circuit board with front and backcard connectors.  The top 3U of the backplane holds 4 row(128 pin) DIN connectors, capable of full 32 bit VME.The first two slots of the backplane use three row (96 pin)DIN connectors in the P1 and P2 positions with thestandard VME pinout.  Thus, a standard VME module canbe inserted in the first two stations. The form factorconversion to the remaining slots is performed on thecustom backplane. The bottom 6U of the backplane, inthe data processing section of the crate, utilizes a singlehigh speed controlled-impedance connector for both frontand rear insertion.  The design is based around a 340 pinconnector, by AMP Inc., to handle the high volume ofdata transmitted from the Receiver cards to the ElectronIsolation and Jet Summary Cards. There are 1419differential 160 MHz point-to-point links on thebackplane between the various cards. The backplane isconstructed with five ground and power planes and fivesignal layers with the differential pairs held to the samelayer.We built a clock and control card to provide thenecessary signals to drive other cards in the crate. Thesignals on even the longest links on this backplanepreserve their characteristics well. Results from testingclock signals on the backplane show rise and fall times of0.8 ns from 20% to 80% height with reasonable signallevels even when measured at the farthest card slot.  Thisperformance meets the requirements of 160 MHz operationof the backplaneFigure 2: Front view of the prototype crate showing theclock and control and electron isolation cards plugged intothe custom backplane.The receiver card is by far the most complicated item inour design. We have built a full scale prototype of thiscard, shown in Figure 3, with large amount of ECLSRAM for lookup tables, support circuitry for three AdderASICs needed on this card and drivers for all backplanelines. In order conserve the board space and to reducepower consumption, the production boards will combinevarious discrete components used to stage the data on intoa multipurpose ASIC that also provides certain cardBoundary Scan functionality. VME, Adder ASIC andinter-crate data sharing circuitry on this card have beentested to function with adequate performance.Figure 3: A picture of the front side of prototype receivercard showing the three Adder ASICs used for making 4x4trigger tower sums used to find jets and determine missingET.The Adder ASIC sums 8  signed 10-bit operands to asingle signed 10-bit result at 160 MHz. We fabricatedprototype adder ASICs which sums eight 10-bit signednumbers in a total of 4 25 ns clock-steps. These ASICs,built by Vitesse in 0.6 µ H-GaAs technology, chosen forits speed and ECL output capability, have been tested towork at 200 MHz, well above our specifications. TheAdder ASIC consists of approximately 11,000 cells anduses 4 W. The tests of the Adder ASIC on the receivercard were successful so that we deemed this design of theAdder as final and are in the process of procuringproduction quantities.3.2 Work in progressThe receiver card uses daughter cards mounted on its rearside to receive its input from calorimeter front-end crates.We have designed these daughter cards with serial linkchips (Vitesse 7214) and associated signal equalizationsupport. These circuits along and an independent test cardare in fabrication. We plan to use these cards to test thefeasibility of receiving data on 20 m long copper cables at1.2 GHz.Success of our Adder ASIC prompted us to select thesame technology for making other ASICs in our system.We have made preliminary designs of Phase ASICdescribed above, Electron Identification ASIC, BoundaryScan/driver ASIC and Sort ASIC and have agreement withVitesse to produce these ASICs. Detailed design work isnow in progress.We are also carrying over the knowledge gained inmaking the prototypes discussed here in designing finalbackplane and other cards. We are incorporating therefinements made to the electron finding algorithm thatresulted in some changes in the dataflow. The Receivercard prototype prompted us to move most of the discretelogic, used on that card to stage data to EID and Jet cards,into the Boundary scan ASIC. Another change we made isto use on card DC-DC converters to distribute neededpower at appropriate voltages.4. SUMMARYWe have made several full scale prototypes of the CMSregional calorimeter trigger system. Successful evaluationof these prototypes has validated key elements of ourdesign. We are in the process of evaluating serial linktechnology that is crucial for the feasibility of the system.Successful validation of tbe Adder ASIC on tbe prototypeReceiver card has prompted us to begin design of all otherASICs required in our system. We have simulated theperformance of this system using detailed Monte Carlo[2]. We believe that this system satisfies the CMSphysics requirements, while meeting the bandwidthrequirements imposed by the data acquisition system. Thisdesign with its extensive use of lookup tables hassufficient flexibility for tuning rates and optimizingefficiencies.5. ACKNOWLEDGEMENTSThis work is supported by grants from the USDepartment of Energy and the University of Wisconsin.                                                [2] S. Dasu et al., CMS calorimeter trigger detailedsimulation, CMS NOTE-1998/027.

CMS calorimeter regional trigger prototypes

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