The parameter-independent design of Phase-Locked Loops (PLLs) is investigated for the case that a bang-bang phase-detector is used. Two self-biased CMOS PLL structures are proposed and compared, one l eading to a completely parameter- and frequency independent behavior. If the PLL frequency operation is constant and known in advance, however, both structures can be made independent of the transisto r Vt and b parameters

Marchioro, A

Moreira, P

Placidi, P

Toifl, Thomas H

CERN Document Server

EUROPEAN ORGANIZATION FOR NUCLEAR RESEARCHCERN–EP/98–4219 February 1998ANALYSIS OF PARAMETER-INDEPENDENT PLLs WITH BANG-BANG PHASE-DETECTORSThomas H. Toifl, Paulo Moreira, Alessandro Marchioro and Pisana PlacidiCERN, EP-Division, CH-1211 Geneva 23, SwitzerlandAbstractThe parameter-independent design of Phase-Locked Loops (PLLs) is investigated for the case that abang-bang phase-detector is used. Two self-biased CMOS PLL structures are proposed andcompared, one leading to a completely parameter- and frequency independent behavior. If the PLLfrequency operation is constant and known in advance, however, both structures can be madeindependent of the transistor Vt and b parameters.(Submitted to  the 5th IEEE International Conference on Electronics, Circuits and Systems,ICECS’98, Lisboa, Portugal)Analysis of Parameter-Independent PLLs withBang-Bang Phase-DetectorsThomas H. Toifl, Paulo Moreira, Alessandro Marchioro and Pisana PlacidiThe Authors are with the Microelectronics group of the European Laboratory for ParticlePhysics (CERN), CH-1211 Geneva 23, and can be reached via e-mail underThomas.Toifl@cern.chAbstractThe parameter-independent design of Phase-LockedLoops (PLLs) is investigated for the case that a bang-bang  phase-detector is used. Two self-biased CMOSPLL structures are proposed and compared, one leadingto a completely parameter- and frequency independentbehavior. If the PLL frequency operation is constantand known in advance, however, both structures can bemade independent of the transistor Vt and b parameters.1. IntroductionPhase-locked loops are a basic element of clock anddata recovery circuits. In order to achieve low jitter,the loop behavior should not depend on variations ofany process parameters, and ideally, should also notchange with frequency. In the case of High EnergyPhysics applications, the devices frequently undergohigh radiation doses leading to substantial deviations ofMOS transistor parameters, especially Vt and •. Hencea loop behavior independent of these parameters isdesirable. A fully self-biased PLL using a standardphase-frequency detector can be found in [1]. In someapplications, e.g. clock recovery, the use of a bang-bang phase detector is more appropriate.This paper investigates how two different CMOS ringoscillator structures, most often used in current PLLs[1][3][4], can be used to achieve process parameterindependence. The first structure uses a simple MOStransistor as voltage-controlled resistor, the second usesa “symmetrical load”, consisting of two equally sizedMOS transistors.2. Bang-Bang Phase Detector PLLsA typical charge-pump PLL is shown in Fig. 1. Abang-bang phase detector consists in the simplest caseof a balanced flip-flop. The input signal is thussampled by the VCO signal, and the decision (eitherearly or late) isderived.CRChargepumpPhase-detector VCOLoop filterVcfreffoutD Qearly/late  Fig. 1.  A typical charge-pump PLL with a bang-bang phase-detector.In contrast to a phase-frequency detector giving asignal proportional to the phase difference between theinput signal and the VCO signal, the decision of abang-bang phase detector is purely binary, leading to anon-linear loop behavior. The bang-bang phase-detector output usually controls a charge-pump, i.e. abi-directional current source, steering a constantcurrent in and out the loop filter. The loop filtertypically consists of a capacitance and a resistorproviding the integral part and the proportional part ofthe loop filter response, respectively.time [cycles]Vc~T1 2 3dVidVpCRIcplate early lateearly   Fig. 2. Typical VCO control voltage behavior using a bang-bang phase detector and an RC-loop filter.A typical behavior of the VCO control voltage Vc canbe seen in Figure 2. Since the changes in the controlvoltage are small, the changes in the loop delay of theVCO are proportional to DVc:cc dVdTVT ⋅∆=∆ . (1)Assuming a constant charge-pump current Icp and acycle time T, the voltage change stemming from theproportional part of the loop filter isRIV cppc .=∆ , (2)and the voltage change from the integral part is.CTIV cpic⋅=∆ (3)The overall change of the loop period during one cyclecalculates toccpcpipdVdTCTIRITTT)( ⋅+⋅==∆+∆=∆(4)3. Parameter Independent Loop BehaviorThere are two different levels of parameterindependence: While the first guarantees a parameterindependent loop behavior for only a single frequency,the other, stricter one, guarantees independence for allfrequencies. In order to achieve stability in a bang-bang PLL, the ratio of the proportional part to theintegral part should be well defined [2]. Hence the firstprinciple of parameter independence for a PLL in abang-bang configuration can be stated as the following:constant/ =∆∆ ip TT , (5)for at least one operation frequency,  independent ofany changes in Vt, • etc.The second principle also demandsconstant./constant,/=∆=∆TTTTip (6)It can be noted from eqs. (2) and (3) that – in contrastto the proportional part - the integral part of the loopfilter response is dependent on the loop cycle time T.Hence, achieving frequency independence is notpossible with a simple RC-loop filter.in1+ in1-out1+out1-VnVcVn. . . 4 x+-Delay stage (4) Replica bias circuitVref   Fig. 3. VCO using single MOS-transistor as VCR.4. Case A: VCO with simple VCRThe first oscillator structure [3] [4] under investigationcan be seen in figure 3. The frequency is controlled viathe gate-source voltage of a PMOS transistor in thetriode region being used as a voltage controlledresistor.  A replica bias circuit keeps the voltage swingconstant. It was verified in SPICE-simulations that therelationship between cycle time T and control voltageVc is fairly accurately given by,  )(Ctcp VVT−= β (7)which can also be derived using a simple analyticalmodel for a pMOS transistor with device trans-conductance bp and threshold voltage Vt.Taking the derivative of eq. (7) gives the linearizeddependence between control voltage and loop delay2)( tcp VVCdVdT−−= β (8)VcIcpC Vdd   Fig. 4. Charge pump current extraction circuit.Dividing eq. (8) by the cycle time T and substitutingthe expression from eq. (7) gives the relative delaysensitivity with respect to the control voltage,tVcVdVdTT −−=11. (9)It can be seen that the relative delay sensitivity onlydepends on the process parameter Vt. To fulfill therequirements of frequency-independence, the followingexpressions, derived from eqs. (1)-(3) and (9), have tobe constant:,1 kVVRITTtccpp=−=∆(10),1 kAVVCTITTtccpi⋅=−=∆ (11)Solving both equations for the charge pump current Icpresults in,)(RVVkI tcpcp−⋅= (12),)(TVVCkI tcicp−⋅⋅= (13)as the required currents for the proportional part andthe integral part, respectively.Substituting the expression for T from eq. (7) in theexpression for the desired current in the integral part,eq. (13),  results in,)( 2tcicp VVkI −⋅⋅= β (14)which is just the well known equation describing thequadratic drain current-vs.-Vgs-behavior in a long-channel MOS transistor.5. Fully Process and frequency independentPLL structureHence, by deriving the charge pump current from acurrent source controlled by the loop control voltage Vcas shown in figure 4, a process and frequencyindependent biasing scheme is obtained for the integralpart of the loop response.To achieve the same frequency-independence for theproportional part the following scheme can be used.The resistor in the loop filter is omitted and the phasedetector is extended, as shown in Fig. 5, in order tosignal when a decision change has occurred (A “late”after a sequence of “early” decision, or vice versa,). Inthe case of a decision change the charge-pump uses aD Qearlyclkchangedearly’   Fig. 5. The early/late difference detection circuit.current Icp’ = • Icp, where a is a constant correspondingto the ratio of the proportional part to the integral partof the loop response. Figure 6 shows the behavior ofthe control voltage when this scheme is used.It should be noted that the proposed structure has alsobeneficial properties with respect to noise coupling tothe oscillator, since the control voltage is now directlyconnected to the high-valued loop-filter capacitance.6. Case B: VCO with “symmetrical load”structureFigure 7 shows the second structure underinvestigation, using “symmetrical load” elements [1] asvoltage controlled resistors. The voltage swing in thedelay elements is regulated by a replica bias circuit inorder to be the same as the VCO control voltage Vc.A formula describing the relationship between controlvoltage Vc and cycle time as T 1/(Vc-Vt) can be foundin [1]. SPICE-Simulations of the oscillator showed,however, that this formula becomes inaccurate forsmall values of Vc-Vt. Using,)( 2tcpcVVVCT−⋅= β (15)to describe the T-vs.-Vc relationship gives fairlyaccurate results, as can be seen in Figure 8.Calculating the relative delay sensitivity from eq. (15)results in:tctcc VVVVVdVdTT −+−=11 (16)Apparently, this formula is much less tractable thaneq. (7). Nevertheless, it turns out that for a broad rangeof frequencies eq. (15) can be approximated by:tc VVdVdTT −−≅11 γ , (17)where g is a constant in the interval [1.4..1.8], depen-ding on the expected ranges of Vc, Vt and Vdd of a givenVCO.Solving again for Icp gives:,)(RVVkI tcpcp−⋅⋅−=γ (18),)(TVVCkI tcicp−⋅⋅⋅−=γ (19)time [cycles]Vc~T1 2 3dVi CIcplate early lateearlyIcp’  Fig. 6. The VCO control voltage behavior using anearly/late difference detection circuit.in1+ in1-out1+out1-VnVcVn. . . 4 x+-Delay stage (4) Replica bias circuit   Fig. 7. VCO structure using symmetrical loads.1 1.5 2 2.5010203040506070Cycle time vs. Vc in symmetrical load VCOVCO control voltage Vc [V]Cycle time [ns]Vc/(Vc-Vt)2     1/(Vc-Vt) [1]    SPICE-simulations   Fig. 8. The relationship between cycle time T and controlvoltage Vc in a symmetrical load VCO.Replacing T from eq. (15) now results in:,)( 3ctcpicp VVVkI−⋅⋅⋅−=βγ(20)which cannot be achieved by a simple circuit. Hence, iffrequency independent biasing has to be considered,structure A should be used.7. Process independent biasing for a singlefrequencyIf, however, the operation frequency is known inadvance, both structures can equally be used togetherwith the simple RC-loop filter described above. Asequations  (12), (13), and (18), (19) show, the requiredcharge pump current Icp is in any case proportional to(Vc-Vt).  To measure Vc-Vt, the circuit shown in Fig. 9RrefVcIcpC   Fig. 9. Simple Vc-Vt  extraction circuit.can be used in the simplest case. Assuming a widePMOS transistor, its gate-source voltage will be veryclose to Vt, producing a current:,)(reftccp RVVI −= (21)In order to achieve higher accuracy, a structure with adifferential amplifier can be used.Substituting the expression for Icp from eq. (21) ineqs.(10) and (11) gives,refpRRTT=∆(22) CRTTTrefi=∆, (23)where the cycle time T now is constant and known inadvance.Hence, the proportional change per cycle can be veryaccurately predicted, since it depends on a ratio ofmatched resistors. Although independent of variationsin Vt and •, the predictability of the integral change percycle is now determined by the process tolerances ofthe available resistors and capacitors in a giventechnology. Since many technologies today providequite narrow tolerances for these parameters (withinthe +/-10% range) this is not a major handicap.8. ConclusionsIn this paper we presented methods to achieveparameter-independent biasing in bang-bang phase-locked loops for two basic differential oscillatorstructures. For the structure using a single transistor asvoltage controlled resistor, we proposed a PLLarchitecture which achieves full process- and frequencyindependence by deriving the charge pump currentfrom the loop control voltage and by extending thephase-detector to signal a decision change. The structure using symmetrical load elements provedto be less suitable for the requirements of full process-and frequency independence caused by its morecomplicated relationship between cycle time andcontrol voltage. By reducing the requirements of thePLL to work at only one frequency we could show thatchoosing a charge-pump current proportional to Vc - Vtleads to independence of transistor parametervariations.9. References [1] J. G. Maneatis, "Low-Jitter Process-Independent DLL andPLL Based on Self-Biased Techniques", IEEE-J. Solid-State Circuits, Vol. 31, No. 11, pp. 1723-1732, Nov. 1996[2] R.J. Walker, C.L. Stout, J.-T. Wu, B. Lai, C.-S. Yen, T.Hornak, P.T. Petruno, “A Two-Chip 1.5GBd Serial LinkInterface”, IEEE-J. Solid-State Circuits, Vol. 27, No. 12,pp. 1805-1810, Dec. 1992[3] S. Kim, K. Lee, Y. Moon, D.-K. Jeong, Y. Choi, H. KyuLim, “A 960Mb/s/pin Interface for Skew-Tolerant BusUsing Low Jitter PLL”, IEEE-J. Solid-State Circuits, Vol.32, No. 5, May 1997[4]   D. Reynolds, “A 320 MHz CMOS Triple 8 bit DAC withOn-Chip PLL and Hardware Cursor”, IEEE-J. Solid-StateCircuits, Vol. 29, No. 12, Dec. 1994

Analysis of parameter-independent PLLs with bang-bang phase-detectors

Abstract

Similar works

Full text

Available Versions

CERN Document Server