research

Triggering and event building results using the C104 packet routing chip

Abstract

The C104 is an asynchronous 32-way dynamic packet routing chip. It has a 264Mbytes/s bi-directional bandwidth and a 1 µsec switching latency. It offers high-density cost- effective commodity communications, which allow large switching networks to be con- structed. Results are presented on the performance of this switching technology within the context of future High Energy Physics level II and level III trigger data traffic patterns

    Similar works