We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm
CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the
top metal layer of the process for the trap electrodes. The process includes
doped active regions and metal interconnect layers, allowing for co-fabrication
of standard CMOS circuitry as well as devices for optical control and
measurement. With one of the interconnect layers defining a ground plane
between the trap electrode layer and the p-type doped silicon substrate, ion
loading is robust and trapping is stable. We measure a motional heating rate
comparable to those seen in surface-electrode traps of similar size. This is
the first demonstration of scalable quantum computing hardware, in any
modality, utilizing a commercial CMOS process, and it opens the door to
integration and co-fabrication of electronics and photonics for large-scale
quantum processing in trapped-ion arrays.Comment: 4 pages, 3 figure

A. M. Eltony

C. D. Bruzewicz

Chiaverini J.

I. L. Chuang

J. Chiaverini

J. M. Sage

K. K. Mehta

Leibrandt D.

R. J. Ram

English

arXiv

Crossref

Applied Physics Letters

Ion traps fabricated in a CMOS foundry

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.United States. Defense Advanced Research Projects Agency. Microsystems Technology OfficeNational Science Foundation (U.S.). Interdisciplinary Quantum Information Science & Engineering (iQuiSE) ProgramUnited States. Dept. of Energy (Science Graduate Fellowship)United States. Intelligence Advanced Research Projects ActivityUnited States. Dept. of Defense. Assistant Secretary of Defense for Research & Engineering (United States. Air Force Contract FA8721-05-C-0002

Mehta, Karan Kartik

Bruzewicz, Colin D.

Sage, Jeremy M.

Chiaverini, John

Eltony, Amira

Chuang, Isaac L.

Ram, Rajeev J

DSpace@MIT

Ion Traps Fabricated in a CMOS FoundryK. K. Mehta,1, a) A. M. Eltony,2, a) C. D. Bruzewicz,3, a) I. L. Chuang,2 R. J. Ram,1 J. M. Sage,3, b) andJ. Chiaverini3, c)1)Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge,Massachusetts 02139, USA2)Center for Ultracold Atoms, Research Laboratory of Electronics and Department of Physics,Massachusetts Institute of Technology, Cambridge, Massachusetts 02139, USA3)Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts 02420,USA(Dated: 17 June 2014)We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. Theprocess includes doped active regions and metal interconnect layers, allowing for co-fabrication of standardCMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layersdefining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loadingis robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This is the first demonstration of scalable quantum computing hardware, inany modality, utilizing a commercial CMOS process, and it opens the door to integration and co-fabricationof electronics and photonics for large-scale quantum processing in trapped-ion arrays.Trapped atomic ions are a promising system forlarge-scale quantum processing1,2, as all required ba-sic quantum operations have been demonstrated withlow error3–5. However, these demonstration experimentstypically consist of relatively few ions (. 10) manipu-lated with optical beams and electronic signals routedfrom outside the ion-trap vacuum chamber. In order toscale the system to the number of quantum bits (qubits)required to provide speedups over classical computingmethods, trap arrays holding orders of magnitude moreions are necessary. Additionally, each array site will re-quire local control, readout electronics, and optics forscalability.Current microfabricated ion traps (and, in fact, re-alizations of any scalable quantum processing technol-ogy) depend on specialized, nonstandard processes in re-search clean-room facilities. The traps are often builtupon non-silicon substrates6,7, and where silicon is used,only a few metal layers (four maximum) have beenimplemented8–15. None of the traps made on silicon sub-strates to date have had doped, active device fabricationavailable, and due to the idiosyncratic process steps used,the lithographic resolution is typically limited. Repeata-bility at different facilities is almost impossible due tolocal process variations and substrate processing capa-bilities.Here we describe the design and operation of an iontrap built into a standard high-resolution CMOS fabri-cation process. Based on industry-standard practices andmaterials, there are active and passive layers beneaththe trap-electrode layer that may enable integration ofa)K. K. Mehta, A. M. Eltony, and C. D. Bruzewicz contributedequally to this work.b)jsage@ll.mit.educ)john.chiaverini@ll.mit.edup-type Si substratepSim5 (ground)m1-m4Al3.9 µm1.3 µm250 nm2.4 µmm6-m8x y5 µm350 nm{{DielectricFIG. 1. (Color online) Die and process cross-section. A mi-crograph of the fabricated 3×3 mm2 die is shown in the upperleft panel. The lower left panel shows a perspective renderingof the top aluminum trap layer and the meshed ground planein copper below, as designed; the gaps in the trap electrodeshere are 5 µm, and the ground mesh is formed of 600 nmwires with 350 nm gaps along x and 10 µm gaps along y. Achip cross section is diagrammed at right, with approximaterelevant dimensions labeled (“pSi” is polysilicon and metalinterconnect layers are labelled m1 through m8). Vias shownbetween metal layers are only representative.electronics and photonics16,17 for control and readoutof trapped-ion quantum states. Standardization of thefoundry process permits any group to produce identicaldevices with high yield.Devices were fabricated on 3 × 3 mm2 die (Fig. 1) ona shared, 300-mm, multi-project wafer produced in a 90-nm CMOS process operated by IBM (9LP process des-arXiv:1406.3643v1  [quant-ph]  13 Jun 20142FIG. 2. (Color online) Micrograph of trap chip diced fromdie and mounted on the sapphire interposer of a cryogenicvacuum system. Aluminum wirebonds are used to make con-tact from the aluminum trap electrodes to the gold interposerleads. The chip is 2.5 mm long and 1.2 mm wide. The insetshows two ions trapped 50 µm from the surface of the trapchip. The ions are approximately 5 µm apart.ignation). This process is primarily utilized for dense,high-performance digital circuits, and the trap die wasone of many designs fabricated in parallel on the samewafer. The process allows for patterning of 8 copper in-terconnect layers, along with the top aluminum pad layer(right panel of Fig. 1). This 1.3 µm thick pad layer wasused for the trap electrodes, and a copper layer (m5) ap-proximately 4 µm below the aluminum layer’s bottomsurface and 2 µm above the silicon substrate was used toform a ground plane under the extent of one of the traps.Due to metal density constraints arising from chemical-mechanical polishing steps applied to these layers, thisground plane was patterned as a mesh of 600 nm stripsseparated by 350 nm along the x direction and 10 µmalong the y direction (see Fig. 1). Metal vias connectthis copper ground plane to the center electrode of thetrap through the upper metal layers m6–m8.We designed and tested linear radio-frequency (RF)surface-electrode18 Paul traps that confine ions 50 µmfrom the electrode surface. The trap has a “five-wire”trap geometry, with two RF electrodes symmetric aboutthe trap axis. Segmented dc control electrodes are routedto the corners of the trap chip to prevent wirebonds fromobstructing laser access (see Fig. 2). This design offersflexibility to create various trapping potentials and allowsscalability to multi-zone traps with complex geometries.Other advantages include comparative ease in selectingcontrol voltages, and relatively narrow RF electrodes, al-lowing for lower capacitive coupling and RF power dissi-pation in the trap. Some inhomogeneity in RF field alongthe trap axis is anticipated due to the short (2 mm) elec-trode length, but effects on trapping are expected to benegligible.A possible limitation to the use of high-resolutionCMOS processing is breakdown at large applied poten-tials, especially since typical ion trap voltage amplitudesare significantly higher than those used in CMOS elec-tronics. However, for up to 200 V static bias applied,the leakage current was below 10 pA, and no sudden in-crease corresponding to a dielectric breakdown was ob-served. We performed these tests at room temperature(in a high-dielectric-strength fluid to prevent air break-down), applying the potential between one of the RFelectrodes and either the ground plane or one of the ad-jacent dc electrodes in both types of trap.After commercial foundry fabrication, trap chips(diced from the full die) approximately 2.5 × 1.2 mm2were bonded to a larger interposer to interface with thecold stage and wiring of a cryogenic vacuum system thatallows for variation of the trap-chip temperature19. Usinga quarter-wave helical resonator, a 43 MHz RF signal ofapproximately 100 V amplitude was applied to the trapelectrodes to produce radial trap frequencies of approxi-mately 4–5 MHz, and an axial potential with frequenciesnear 1 MHz was produced by application of dc potentialsof up to approximately 30 V to the segmented controlelectrodes. We load 88Sr+ ions by accelerating precooledSr atoms from a magneto-optical trap toward the iontrap where they are photo-ionized and Doppler cooled19.Although not measured precisely in this work, loading ef-ficiency into these traps is similar to more conventionallyfabricated surface-electrode traps using the same loadingmethod.Traps without a ground plane displayed significantlaser-induced photo-effects due to the excitation of car-riers in the silicon by scattered light used for atomphotoionization (PI, 405 nm) and ion Doppler cooling(422 nm). During trap loading, this manifested itself asvariation of the RF voltage amplitude on the trap elec-trodes due to varying impedance of the trap when the405-nm PI light was on. The effects on the trappingpotential were visible as ion motion synchronized to thePI light switch state. We observed no photo-effects intraps with a ground plane. Traps without a ground planealso exhibit strong trap-temperature-dependent nonlin-earities in the resonance response of the voltage-step-upresonator. A ground plane reduces RF leakage into thesilicon substrate sufficiently to eliminate this effect, suchthat we observed stable trapping for chip temperaturesfrom 300 K down to 8 K. We noticed slightly more powerdissipation in the foundry traps than in traps fabricatedfrom gold or niobium on sapphire for similar RF volt-age amplitude20, most likely due to higher dissipation inthe metals or dielectrics. Ion lifetimes of more than anhour were observed in the presence of Doppler coolinglight, equivalent to the best lifetimes seen in other trapsmeasured in this vacuum system.Excess micromotion (ion motion at the RF drive fre-quency) is caused by static electric fields that displacethe ion from the RF null and can lead to ion heating.We compensate for this micromotion using the standard30.60.40.20.0Average vibrational quanta6543210Probe pulse delay [ms]1008060Heating rate [quanta/s]43210Experimental trialFIG. 3. (Color online) Representative measurement of heat-ing rate in a CMOS-foundry-fabricated ion trap. Averageoccupation of the axial mode of vibration in the linear trapis plotted as a function of delay time after preparation in theground state at a trap temperature of 8.4 K. A linear fit (lineshown) gives a heating rate for these data of 80(5) quanta/swhere the uncertainty is due to statistical errors propagatedthrough the fit. An average of five such measurements gives aheating rate of 81(9) quanta/s where the uncertainty is due torun-to-run variability. The inset shows all five measurementswith a line indicating the weighted average value.method of applying an additional opposing static field.Typical stray field values are on the order of 500 V/mhere and appear stable over days. Although silicon ox-ide dielectric is exposed at the locations of gaps in theelectrodes and may charge due to laser-induced photo-electron production, the stray field’s stability suggestsanother cause. Wirebonds, which are asymmetric withrespect to the ion location and also closer to the ionhere than in the case of larger trap chips, may be re-sponsible for the steady stray electric field. The use ofthrough-silicon-via technology can eliminate wirebondsfrom the chip surface, as has recently been demonstratedfor surface-electrode ion traps21.When compared to single-metal-layer traps (SMLTs)on sapphire substrates, these traps exhibit increased scat-ter of laser light, possibly due to higher as-depositedroughness of the aluminum layer. We examined the trap-electrode surface using atomic force microscopy and mea-sured an RMS roughness of 35 nm, significantly largerthan the 2 nm we have measured on SMLTs. Scatterfrom the surface can be reduced by focusing laser beamsto a smaller diameter at the trap.Trapped-ion multi-qubit quantum operations can belimited by electric field noise that heats the ions’ sharedvibrational modes in the trap, reducing gate fidelity22,23.Anomalously large heating rates caused by unknownnoise sources have been seen in every trapped-ion exper-iment that has examined motional-state heating. Thisis particularly noticeable in small microfabricated trapsas the heating rate appears to scale as 1/d4 for an ion adistance d from a trap electrode surface. It is thereforeimportant to characterize the heating rate in potentiallyscalable trap technologies.Using the dipole-forbidden S1/2 → D5/2 transition in88Sr+, we performed resolved-sideband cooling to pre-pare the ion in the ground state (average occupationn¯ ≈ 0.05) of the 1.3 MHz axial vibrational mode andthen measured the heating rate using sideband amplitudespectroscopy on this transition after a varying delay20.Results of one such measurement are presented in Fig. 3for a chip temperature of 8.4 K. Five measurements wererecorded over a few days for nominally the same condi-tions; the average heating rate is 81(9) quanta/s. Whenscaled by 1/d4 to compare traps of different sizes, thisheating rate is lower than that reported in any othertrap fabricated on a silicon substrate8,9,11,12,14,24. Mo-tional heating at this level would lead to an error of lessthan 10−2 in a 100 µs two-ion-qubit gate, below the fault-tolerance threshold for large scale quantum computingwith surface-code error-correction schemes25.We have shown basic functionality for quantum pro-cessing using a fabrication process, without modification,that has enabled scaling to billions of transistors. This isthe first demonstration, in any physical implementation,of quantum computing hardware co-fabricated with scal-able classical computing hardware. The fabrication of ad-vanced CMOS and photonic technology on the trap chip,including the extensive existing libraries of integrated cir-cuits for digital logic and memory, offers a straightfor-ward path to scalable, local optical and electronic controland readout of trapped-ion arrays. The demonstration ofstable trapping and low electric-field noise in a foundry-process trap is therefore an initial step toward integrationof the required classical computing and photonic devicesfor useful, large-scale quantum processing with trappedions.ACKNOWLEDGMENTSWe thank Peter Murphy, Chris Thoummaraj, andKaren Magoon for assistance with ion-trap-chip packag-ing at Lincoln Laboratory. K.K.M. and R.J.R acknowl-edge funding from DARPA MTO, NSF iQuISE, and aDOE Science Graduate Fellowship. I.L.C. acknowledgesfunding from IARPA. The work at Lincoln Laboratoryis sponsored by the Assistant Secretary of Defense forResearch & Engineering under Air Force contract num-ber FA8721-05-C-0002. Opinions, interpretations, con-clusions, and recommendations are those of the authorsand are not necessarily endorsed by the United StatesGovernment.1D. Leibfried, R. Blatt, C. Monroe, and D. Wineland, Rev. Mod.Phys. 75, 281 (2003).2R. Blatt and D. Wineland, Nature 453, 1008 (2008).43J. Benhelm, G. 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Ion traps fabricated in a CMOS foundry

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