Instruction Re-selection for Iterative Modulo Scheduling on High Performance Muti-issue DSPs

Abstract

Abstract. An iterative modulo scheduling is more important for compilers targeting high performance multi-issue digital signal processors than ever before because these processors are often severely limited by idle state functional units due to dependence constraint and thus the reduced the idle units can have a positively significant impact on their performance. However, complex instructions, which are used in most recent DSPs such as mac, usually increase a data dependence complexity, and such complex dependencies that exist in signal processing applications often restrict modulo scheduling freedom and therefore, become a limiting factor of the iterative modulo scheduler. In this work, we propose a novel technique that efficiently reselect instructions of an application loop code considering with dependence complexity, which directly resolve the dependence constraint on a loop body, that are specifically featured for accelerating software pipelining performance by minimizing length of intrinsic cyclic dependencies in a loop code. To take advantage of this feature, few existing compilers support a loop unrolling based dependence relaxing technique, but only use them for some limited cases. This is mainly because the loop unrolling typically occurs an overhead of huge code size increment, and the iterative modulo scheduling with relaxed dependence techniques for general cases is an NP-hard problem that necessitates complex assignments of registers and functional units in resource reservation table [8]. Our technique uses a heuristic to efficiently handle this problem in pre-stage of iterative modulo scheduling without loop unrolling. key words: code generation and optimization, application specific embedded software design, software pipelining, dependence analysis, high performance DSPs