Design of low power 4-tap 8-bit adiabatic FIR filter

Abstract

Abstract — Digital signal processing (DSP) is used to perform filtering, decimation and down conversion in common communications systems, like in oversampling analog to digital converters in wireless and audio applications. This paper describes a design of low order FIR (finite impulse response) filters to be used at the high sampling rates for achieving a low power DSP implementation. This paper reviews the asymptotic zero energy dissipation techniques named as Adiabatic switching logic. The Adiabatic switching technique beats the dynamic power as well as short circuit power, using recycling of energy stored on circuit capacitances instead of dissipating it as heat. PAL technique is the simplest fully adiabatic technique requiring lesser number of power clocks as well as area. Design of four tap 8-bit fully pipelined FIR filter, using PAL adiabatic technique and CMOS technique is compared at different operating frequencies from 5 MHz to 100 MHz, the range which includes input sampling rate for GSM (10 MS/s) and DECT (50 MS/s) standards. Comparison also includes the power loss in adiabatic power supply. Using 0.25 µm technology and 3.3 V voltage supply, energy saving in PAL compared to CMOS is 3 times to 15 times, with frequency varied from 100MHz down to 5MHz. I