A Reconfigurable Coprocessor for Redundant Radix-4 Arithmetic Abstract

Abstract

We present the implementation of a reconfigurable arithmetic coprocessor based on a fast parallel multiplication scheme proposed in [1]. In this coprocessor, we have implemented four basic arithmetic operations (viz. addition, subtraction, multiplication and complementation) and four primary logic operations (viz. AND, OR, EX-OR and NOT). The coprocessor can be directly accessed from the PC by an interfacing software implemented in [19]. In this project, we have developed a complete set of VHDL modules, which through different stages of Xilinx Foundation Express 3.1i, finally give rise to the bitstream file which is downloaded from the PC to the FPGA board to configure the FPGA chip (target architecture: XC4010E TM) as the desired arithmetic coprocessor. Acknowledgement In the beginning, we would like to pay our sincerest thanks and gratitude to Prof. Bhabani P. Sinha for allowing us to use his paper on “Fast Parallel multiplication using redundant quarternary number system ” [1] for FPGA implementation. We would also like to acknowledge here the thesis work by Koushik Sinha [20] as the first step towards FPG