Analysis of Sub-block Placement and Victim Caching Techniques

Abstract

Rapid advances in computer technology have led to the development of processors with peak performances of the order of GHz. Since it is not feasible to have unlimited fast-memory, the performance of these processors is handicapped if the performance of the memory-hierarchy is poor. Caching techniques have been developed with this in mind. This paper presents the analysis of the performance of two such techniques. Sub-block placement: This technique reduces the miss penalty by reducing the bandwidth between the cache and it’s next level. Our results show that sub-block placement enhances the performance both for L1 and L2, more significantly in the former. The performance improves with the increase in the number of subblocks. Victim caching: This technique reduces the miss rate by adding a small, fully associative cache between a cache and the next level in the memory hierarchy. The results show that victim caches reduce the miss rate in L1 caches, but the reduction achieved depends on the structure and configuration of the cache and it’s victim cache. Our study of the performance of victim caches as the block size, cache size and associativity of the caches was varied showed that there can be a significant improvement in performance. However, as cache sizes increase or associativity becomes higher, victim caches do not greatly enhance performance