On-chip stochastic communication

Abstract

As CMOS technology scales down into the deep-submicron (DSM) domain, the Systems-On-Chip (SoCs) are becoming increasingly complex and the costs of design and verification are rap-idly increasing due to the inefficiency of traditional CAD tools. Relaxing the requirement of "100 % correctness " for devices and interconnects drastically reduces the costs of design but, at the same time, requires that SoCs be designed with some degree of system-level fault-tolerance. This thesis introduces a novel communication paradigm for SoCs, called stochastic communication. The newly proposed scheme not only separates communication from computation, but also pro-vides the required built-in fault-tolerance to DSM failures, is scalable and cheap to implement. For a generic network-on-chip (NoC) architecture, we show how a ubiquitous multimedia application (an MP3 encoder) can be implemented using stochastic communication in an efficient and robust manner. More precisely, by using this communication scheme, up to 70 % data upsets, 80 % packet losses because of buffer overflow, and severe levels of synchronization failures can be tolerated, while providing a much lower latency than a traditional, bus-based implementation. The present thesis also introduces a new concept, called on-chip diversity, which means mix-ing different architectures and/or technologies in a multiple voltage/frequency island setup in order to achieve the highest levels of performance, fault-tolerance, and the needed flexibility in SoC design. We outline how stochastic communication can enable the overall integration of such systems, and how it can become the base for several hybrid communication architec-tures. We believe that the ideas and the results presented here will open up a whole new area of research with deep implications for on-chip network design and the future generations of SoCs