Parsing using the PARSEC Vector Processing Chip

Abstract

This paper describes the implementation of the PARSEC 1 chip, a vector processing element (PE) for parsing languages. This chip has applications not only in natural language processing, but can also be applied to other constraint satisfaction problems. The PARSEC chip is based on a parsing algorithm which formerly ran in real time on a massively parallel machine [4]; however, the chip can achieve processing speeds fast enough for real-time language processing systems, while at the same time, having a price and form suitable for mass market applications. Key Words: artificial intelligence architectures and applications, VLSI A key component of any natural language interface is its parsing algorithm. Because some features of English (e.g., context) are clumsy or impossible to handle using existing parsers, we have extended and implemented a parsing algorithm based on a new, flexible grammatical formalism, called Constraint Dependency Grammar (CDG), introduced by Maruyama [5, 6, 7]. Th..