Balancing logic utilization and area efficiency in FPGAs

Abstract

Abstract. In this paper we outline a procedure to determine appropriate partitioning of programmable logic and interconnect area to minimize overall device area across a broad range of benchmark circuits. To validate our design approach, FPGA layout tools which target devices with less that 100 % logic capacity have been developed to augment existing approaches that target fully-utilized devices. These tools have been applied to FPGA and reconfigurable computing benchmarks which range from simple state machines to pipelined datapaths. In general, it is shown that the minimum area point for architectures similar to those available from Xilinx Corporation falls below the 100 % logic utilization point for many circuits.