Small Delay Defect Detection Using Self-Relative Timing

Abstract

A novel testing strategy is proposed that is designed to detect small delay defects by creating internal signal races. The races are created by launching transitions along two paths simultaneously, a reference path and a test path. The arrival times of the transitions on a common or ‘convergence’ gate determine the result of the race. The presence of a small delay defect on the test path creates a static hazard on the output of the convergence gate that is directed to the input of a scan-latch. A glitch detector is added to the scan latch to record the presence or absence of the glitch. Advancement of technology to nanometer feature sizes and new materials is changing the pareto of defect types, making defects such as resistive open vias, mouse bites an