Improved Design Methodology for High-Speed High-Accuracy Current Steering D/A Converters

Abstract

This paper describes a sizing and design methodology for high-speed high-accuracy current steering D/A converters taking into account mismatching in all the transistors of the current source cell. The presented method allows a more accurate selection of the optimal design point without introducing arbitrary safety margins, as was done in the previous literature. This methodology has been applied to the design of a CMOS 12-bit 400 MHz current-steering segmented D/A converter. Commercial CAD tools are used to automatically lay out regular structures of the DAC, specially the current source array, following an optimal twodimensional switching scheme to compensate for systematic mismatch errors.