Abstract COMPILING DATAFLOW PROGRAMS FOR DIGITAL SIGNAL PROCESSING

Abstract

The synchronous dataflow (SDF) model has proven efficient for represent-ing an important class of digital signal processing algorithms. The main property of this model is that the number of data values produced and consumed by each computation is fixed and known at compile-time. This thesis develops techniques to compile SDF-based graphical programs for embedded signal processing appli-cations into efficient uniprocessor implementations on microprocessors or pro-grammable digital signal processors. The main problems that we address are the minimization of code size and the minimization of the execution time and storage cost required to buffer intermediate results. The minimization of code size is an important problem since only limited amounts of memory are feasible under the speed and cost constraints of typical embedded system applications. We develop a class of scheduling algorithms that minimize code space requirements without sacrificing the efficiency of inline code. This is achieved through the careful organization of loops in the target pro-