Automated Correctness Condition Generation for Formal Verification of Synthesized RTL Designs

Abstract

High-level synthesis tools generate register-transfer level designs from algorithmic behavioral specifications. High-level synthesis process typically consists of dependency graph scheduling, functional unit allocation, register allocation, interconnect allocation and controller generation tasks. Widely used algorithms for these tasks retain the overall control flow structure of the behavioral specification allowing code motion only within basic blocks. Further, high-level synthesis algorithms are oblivious to the mathematical properties of arithmetic and logic operators. Selecting and sharing of rtl library modules are solely based on matching uninterpreted function symbols and constants. Many researchers have noted that these features of high-level synthesis algorithms can be exploited to develop efficient verification strategies for synthesized designs. This paper reports a verification technique that effectively exploits these features to achieve efficient and fully automated verification of synthesized designs and its incorporation in a high-level synthesis tool