Design of a comparator in a 0.25m CMOS technology.

Abstract

A comparator for the LHCb readout chip, the Beetle, has been designed in a 0.25m CMOS technology and is sent for fabrication. To improve threshold uniformity, each comparator has a 3 bits DAC. The comparator can handle positive and negative input signals. A polarity signal changes the polarity of the threshold level and makes the output signal always active high. The output signal is latched by a 40MHz clock and is selectable between time-over-threshold mode (in 25ns bins) and one pulse mode (25ns). Simulation results will be discussed in section II