Task-level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures

Abstract

This paper presents spade, a system for partitioning designs onto multi-fpga architectures. The input to spade is a task graph, that is composed of computational tasks, memory tasks and the communication and synchronization between tasks. spade consists of an iterative partitioning engine, an architectural constraint evaluator, and a throughput optimization and rtl design space exploration heuristic. We show how various architectural constraints can be effectively handled using an iterative partitioning engine. 1 Introduction The primary focus of existing multi-fpga partitioning research is rtl or gate level partitioning. A popular and advantageous system-synthesis approach is to perform behavioral partitioning prior to, or during, the high-level synthesis process [1]. Although several interesting features may be found in existing multi-fpga partitioning techniques, it is very difficult to adapt any of them to suite partitioning for a generic multi-fpga board. This is because, stateo..