A Comparative Study of DSP Multiprocessor List Scheduling Heuristics

Abstract

This paper presents a quantitative comparison of a collection of DSP multiprocessor list scheduling heuristics which consider inter-processor communication delays. The following aspects have been addressed: (1) performance in terms of the total execution time (makespan), (2) sensitivity of heuristics in terms of the characteristics of acyclic precedence graphs, including graph size and graph parallelism, (3) sensitivity of heuristics to the number of processors, and (4) compile time efficiency. In addition, the effectiveness of list scheduling performance enhancement techniques is examined. The main contributions of this paper are: ffl Contrary to the belief of some previous authors, our study indicates that no single published list scheduling heuristic consistently produces the best schedules under all possible program structures and DSP multiprocessor configurations. We believe this fact is very important to designers of DSP multiprocessor scheduling heuristics. ffl Based on such o..