Recursive and Repetitive Hardware Models in VHDL

Abstract

In this report, techniques for developing VHDL descriptions of recursive hardware structures are examined. In particular, both recursive and repetitive component instantiations are examined for modeling recursive structures. This report examines two example structures: a fanout tree of buffers and a fat tree interconnection network. For both structures, the recursive descriptions are easier to develop, and more clearly express the structure, making them easier to understand. The main difficulty in developing repetitive structures lies in devising a way of interconnecting the basic components comprising the structure. It is shown that the difficulties result from fundamental language design decisions made in VHDL, and that it is not appropriate to modify the language to avoid the difficulties. Hence, in general, the recursive style is preferred over the repetitive style for describing recursive hardware structures. 1 1. Introduction Many of the hardware structures that are designed ..