Issues of Advanced Architectural Features in the Design of a Timing Tool

Abstract

This paper describes a timing tool being developed by a real-time research group at Seoul National University. Our focus is on the issues resulting from advanced architectural features such as pipelined execution and cache memories found in many modern RISC-style processors. For each architectural feature we state the issues and explain our approach. 1 Introduction In real-time computing systems, tasks have timing requirements (i.e., deadlines) that must be met for correct operation. Various scheduling techniques have been proposed to guarantee such timing requirements. In many cases, these scheduling techniques require that the worst case execution times (WCETs) of tasks be known a priori. This paper describes a timing tool that is being developed by a real-time research group at Seoul National University. This timing tool aims at accurately calculating guaranteed worst case execution times of programs for computer systems that use modern RISC-style microprocessors. Our particular fo..