This paper considers the problem of register communication in the Multiscalar architecture, a novel paradigm for exploiting instruction level parallelism. The Multiscalar architecture employs a combination of hardware and software mechanisms to partition a sequential program into tasks, and uses control and data speculation to execute such tasks in parallel. Inter-task register dependencies represent register communication in the architecture. The two primary issues in register communication for a Multiscalar processor are correctness and performance. Not only must proper values be directed from producers to consumers, these values must be sent as early as possible from producing tasks to consuming task in order to avoid execution stalls which may have a critical impact on overall performance. We present a simple model to ensure that register communication obeys the sequential semantics of the program. To this model, we apply a progression of hardware techniques (including register dat..
