Memory Models

Abstract

this memory usually consists of highly-interleaved SRAM, and is a major---perhaps the dominant---component in the cost of these machines. Even so, supercomputer compilers must employ aggressive prefetching techniques, and supercomputer processors must be prepared to execute instructions out of order, to hide the latency of memory. Current hardware and software trends suggest that caches are likely to become more effective for future supercomputer workloads. Hardware trends include the development of very large caches with multiple banks, which address the bandwidth problem. Software System Node System Node System Node processor processor processor processor processor processor memory memory memory Interconnect memory memory memory Interconnect Distributed Memory Architecture Dance-hall Memory Architecture Figure 0.2: Simplified Distributed and Dance-Hall Memory Architecture Multiprocessors trends include the development of compilers that apply techniques such as blocking [7] to increase locality of reference. Independent of the existence of caches, designers must address the question of where to locate main memory. They can choose to co-locate a memory module with each processor or group of processors, or to place all memory modules at one end of an interconnection network and all processors at the other. The first alternative is known as a distributed memory architecture; the second is known as a dance-hall architecture