Datapath-oriented FPGA Mapping and Placement for Configurable Computing (Extended Abstract)

Abstract

Timothy J. Callahan and John Wawrzynek University of California--Berkeley Widespread acceptance of FPGA-based reconfigurable coprocessors will be expedited if compilation time for FPGA configurations can be reduced to be comparable to software compilation. This research achieves this goal, generating complete datapath layouts in fractions of a second rather than hours. Our algorithm, adapted from instruction selection in compilers, packs multiple operations into single rows of CLBs when possible, while preserving a regular bit-slice layout. Furthermore, placement and thus routing delays are considered simultaneously with packing, so that the total delay, not just the CLB delay, is optimized. The Problem Reconfigurable coprocessors, most commonly implemented with field programmable gate array (FPGA) technology, have been shown effective in accelerating certain classes of applications. Computation-intense kernels can be selected automatically or by hand for acceleration using the coproc..