Transformations and Resynthesis for Testability of RT-Level Control-Data Path Specifications

Abstract

This paper introduces a technique to transform a given RT-Level design, consisting of control logic and data path, into a functionally equivalent, minimized design which is 100% testable under full-scan at the gate level. The proposed RT-Level optimization technique uses the RT-Level structure and exploits the interaction between the control and the data path. Our approach maintains the RT-Level design hierarchy while performing RT-Level transformations of initially specified data path, followed by resynthesis of control using don't cares extracted from the data path. Experiments with several RTL benchmarks demonstrate the effectiveness of the technique in generating fully testable designs. In addition, comparison with logic-level techniques show the advantages of the proposed technique as an optimizing tool to produce circuits with reduced area and delay. 1 Introduction The goal of behavioral synthesis is to produce a RTL hardware description that meets various design constraints. Th..