Code Generation for Dual-Load-Execute Architectures

Abstract

This paper studies the problem of register allocation and scheduling for Dual-LoadExecute (DLE) architectures. These are architectures which can execute an ALU instruction and two memory transfer operations (load/store) in a single instruction cycle. DLE architectures are extensively used in the design of Digital Signal Processors (DSPs) like the Motorola 56000, Analog Devices ADSP-2100, and NEC ¯PD77016. This work proves the existence of an efficient O(n) expression tree code generation algorithm for DLE architectures which have homogeneous register sets. The algorithm is an extension of the Sethi-Ullman algorithm, and produces guaranteed optimal code for a large number of expression trees in the program. The experimental results, using the NEC ¯PD77016 as the target processor, show the efficacy of the approach. 1 Introduction Digital Signal Processors (DSPs) are receiving increased attention recently due to their role in the design of modern embedded systems like video cards, ce..