Effects Of Main Memory Latencies On The Performance Of Nonblocking Caches

Abstract

Lockup-free caches in conjunction to non-blocking processor loads have been proposed to hide miss latencies in high performance processors. One problem with current approaches is the increased complexity of the processor and of the cache controller due to non-blocking. In this paper, we introduce a simple mechanism to support non-blocking loads and a lockup-free cache. A modified SPARC architecture with non-blocking loads and support for the new mechanism has been simulated. To be effective the architecture also needs compiler support. Five fortran do-loops are selected and transformed with simple software pipelining techniques to drive the simulator. The simulator is used to investigate the effectiveness of the architecture and the compiler transformations at hiding miss latencies up to 200 processor cycles. For a given program after transformation we identify a critical latency. We show that for lower latencies the cache is effective by simply overlapping misses with processor execut..