The Mermaid Architecture-workbench for Multicomputers

Abstract

Cache hierarchy Bus Figure 3: The template architecture models. defines a bus component. It is a simple forwarding mechanism, carrying out arbitration upon multiple accesses. The parameters used to configure this component include buswidth, bus cycle-time and arbitration details. Changing the bus to a more complex structure, such as a multistage network, can be done without too much remodelling effort. In that case, only a new Pearl module needs to be written, replacing the bus component within the template model. Finally, the memory component simulates a simple DRAM memory. It is parameterized with memory size, memory refresh rate, and memory access latencies. 4.2 Multi-node communication model A node within the communication template model is constructed from an abstract processor, a router and multiple communication links. This setup is shown in Figure 3(b). The nodes are connected in a topology that reflects the physical interconnection scheme of the multicomputer, resulting in ..