Standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 1.2 Features and benefits � Low conduction losses due to low on-state resistance � Suitable for high frequency applications due to fast switching characteristics 1.3 Application

Conditions Min

General Description

Quick Reference

Symbol Parameter

Typ Max Unit

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PHB66NQ03LT
N-channel TrenchMOS logic level FET
Rev. 07 — 30 January 2009 Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic 
package using TrenchMOS technology. This product is designed and qualified for use in 
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
 Low conduction losses due to low 
on-state resistance
 Suitable for logic level gate drive 
sources
1.3 Applications
 DC-to-DC convertors  General purpose switching
1.4 Quick reference data
 
Table 1. Quick reference
Symbol Parameter Conditions Min Typ Max Unit
VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 25 V
ID drain current Tmb =2 5° C ;  V GS = 1 0 V --6 6 A
Ptot total power 
dissipation
Tmb = 25 °C; see Figure 2 --9 3 W
Dynamic characteristics
QGD gate-drain charge VGS =5V ;  I D =5 0A ;  
VDS =1 5V ;  T j =2 5° C ;
see Figure 11
-3 . 6 -n C
Static characteristics
RDSon drain-source 
on-state resistance
VGS =1 0V ;  I D =2 5A ;  
Tj = 25 °C; see Figure 9;
see Figure 10
- 9.1 10.5 mΩPHB66NQ03LT_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 30 January 2009 2 of 13
NXP Semiconductors PHB66NQ03LT
N-channel TrenchMOS logic level FET
2. Pinning information
 
[1] It is not possible to make a connection to pin 2.
3. Ordering information
 
Table 2. Pinning information
Pin Symbol Description Simplified outline Graphic symbol
1G g a t e
SOT404                             
(D2PAK)                         
2D d r a i n [1]
3S s o u r c e
mb D mounting base; connected to 
drain
mb
13
2
S
D
G
mbb076
Table 3. Ordering information
Type number Package
Name Description Version
PHB66NQ03LT D2PAK plastic single-ended surface-mounted package (D2PAK); 3 leads (one 
lead cropped)
SOT404PHB66NQ03LT_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 30 January 2009 3 of 13
NXP Semiconductors PHB66NQ03LT
N-channel TrenchMOS logic level FET
4. Limiting values
 
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 25 V
VDGR drain-gate voltage Tj ≥ 25 °C; Tj ≤ 175 °C; RGS =2 0k Ω -2 5 V
VGS gate-source voltage -20 20 V
ID drain current VGS =1 0V ;  T mb =1 0 0° C - 4 5 A
VGS =5V ;  T mb = 100 °C; see Figure 1 -4 0 A
VGS =5V ;  T mb =2 5° C ;  s e e  Figure 1;
see Figure 3
-5 7 A
VGS =1 0V ;  T mb =2 5° C - 6 6 A
IDM peak drain current tp ≤ 10 µs; pulsed; Tmb =2 5° C ;  s e e  Figure 3 -2 2 8 A
Ptot total power dissipation Tmb =2 5° C ;  s e e  Figure 2 -9 3 W
Tstg storage temperature -55 175 °C
Tj junction temperature -55 175 °C
Source-drain diode
IS source current Tmb =2 5° C - 5 7 A
ISM peak source current tp ≤ 10 µs; pulsed; Tmb =2 5° C - 2 2 8 A
Avalanche ruggedness
EDS(AL)S non-repetitive 
drain-source avalanche 
energy
VGS =1 0V ;  T j(init) =2 5° C ;  I D =4 3A ;  V sup ≤ 25 V; 
unclamped; tp = 0.15 ms; RGS =5 0Ω
-9 0 m JPHB66NQ03LT_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 30 January 2009 4 of 13
NXP Semiconductors PHB66NQ03LT
N-channel TrenchMOS logic level FET
 
Fig 1. Normalized continuous drain current as a 
function of mounting base temperature
Fig 2. Normalized total power dissipation as a 
function of mounting base temperature
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
Tmb (°C)
0 200 150 50 100
03aa24
40
80
120
Ider
(%)
0
Tmb (°C)
0 200 150 50 100
03aa16
40
80
120
Pder
(%)
0
03ag19
      1
    10
  10
2
  10
3
   1   10  10
2
VDS (V)
ID
(A) tp = 10 μs
DC
100 ms
10 ms
Limit RDSon = VDS  / ID
1 ms
100 μsPHB66NQ03LT_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 30 January 2009 5 of 13
NXP Semiconductors PHB66NQ03LT
N-channel TrenchMOS logic level FET
5. Thermal characteristics
 
 
Table 5. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Rth(j-a) thermal resistance from 
junction to ambient
mounted on a printed-circuit board; 
minimum footprint; vertical in still air
-5 0 -K / W
Rth(j-mb) thermal resistance from 
junction to mounting 
base
see Figure 4 --1 . 6 K / W
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
03ag18
10
-2
10
-1
      1
    10
10
-5 10
-4 10
-3 10
-2 10
-1    1   10
tp (s)
Zth(j-mb)
(K/W)
single pulse
δ = 0.5
0.2
0.1
0.05
0.02
tp
T
P
t
tp
T
δ =PHB66NQ03LT_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 30 January 2009 6 of 13
NXP Semiconductors PHB66NQ03LT
N-channel TrenchMOS logic level FET
6. Characteristics
 
Table 6. Characteristics
Symbol Parameter Conditions Min Typ Max Unit
Static characteristics
V(BR)DSS drain-source 
breakdown voltage
ID =2 5 0µ A ;  V GS =0V ;  T j =- 5 5° C 2 2 - - V
ID =2 5 0µ A ;  V GS =0V ;  T j =2 5° C 2 5 - - V
VGS(th) gate-source threshold 
voltage
ID =1m A ;  V DS = VGS; Tj =- 5 5° C ;
see Figure 7; see Figure 8
--2 . 2 V
ID =1m A ;  V DS = VGS; Tj = 175 °C;
see Figure 7; see Figure 8
0.5 - - V
ID =1m A ;  V DS = VGS; Tj =2 5° C ;
see Figure 7; see Figure 8
11 . 5 2V
IDSS drain leakage current VDS =2 5V ;  V GS =0V ;  T j = 2 5 ° C --1 0 µ A
VDS =2 5V ;  V GS =0V ;  T j = 175 °C - - 500 µA
IGSS gate leakage current VGS =1 5V ;  V DS =0V ;  T j = 25 °C - 10 100 nA
VGS =- 1 5V ;  V DS =0V ;  T j = 25 °C - 10 100 nA
RDSon drain-source on-state 
resistance
VGS =1 0V ;  I D =2 5A ;  T j = 175 °C;
see Figure 9; see Figure 10
- 16.4 18.9 mΩ
VGS =5V ;  I D =2 5A ;  T j =2 5° C ;
see Figure 9; see Figure 10
-1 1 . 2 1 3 . 6 m Ω
VGS =1 0V ;  I D =2 5A ;  T j =2 5° C ;
see Figure 9; see Figure 10
-9 . 1 1 0 . 5 m Ω
Dynamic characteristics
QG(tot) total gate charge ID =5 0A ;  V DS =1 5V ;  V GS =5V ;  
Tj =2 5° C ;  s e e  Figure 11
-1 2 -n C
QGS gate-source charge - 4.5 - nC
QGD gate-drain charge - 3.6 - nC
Ciss input capacitance VDS =2 5V ;  V GS = 0 V; f = 1 MHz; 
Tj =2 5° C ;  s e e  Figure 12
- 860 - pF
Coss output capacitance - 330 - pF
Crss reverse transfer 
capacitance
- 145 - pF
td(on) turn-on delay time VDS =1 5V ;  R L =0 . 6Ω; VGS =5V ;  
RG(ext) =5 . 6Ω; Tj =2 5° C
-1 5 2 5 n s
tr rise time - 90 135 ns
td(off) turn-off delay time - 25 40 ns
tf fall time - 25 40 ns
Source-drain diode
VSD source-drain voltage IS =2 5A ;  V GS =0V ;  T j =2 5° C ;
see Figure 13
- 0.95 1.2 V
trr reverse recovery time IS =1 0A ;  d I S/dt = -100 A/µs; VGS =0V ;  
VDS =2 5V ;  T j =2 5° C
-3 2 -n s
Qr recovered charge - 20 - nCPHB66NQ03LT_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 30 January 2009 7 of 13
NXP Semiconductors PHB66NQ03LT
N-channel TrenchMOS logic level FET
 
Fig 5. Output characteristics: drain current as a 
function of drain-source voltage; typical values
Fig 6. Transfer characteristics: drain current as a 
function of gate-source voltage; typical values
Fig 7. Gate-source threshold voltage as a function of 
junction temperature
Fig 8. Sub-threshold drain current as a function of 
gate-source voltage
03ag20
0
20
40
60
80
0 0.5 1 1.5 2
VDS (V)
ID
(A)
5 V Tj = 25 °C
VGS = 3 V
10 V
3.5 V
6 V
4 V
4.5 V
03ag22
0
20
40
60
80
012345
VGS (V)
ID
(A)
VDS > ID x RDSon
Tj = 25 °C 175 °C
03aa33
0
0.5
1
1.5
2
2.5
-60 0 60 120 180
Tj (°C)
VGS(th)
(V)
max
typ
min
03aa36
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
0123
VGS (V)
ID
(A)
max typ minPHB66NQ03LT_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 30 January 2009 8 of 13
NXP Semiconductors PHB66NQ03LT
N-channel TrenchMOS logic level FET
Fig 9. Drain-source on-state resistance as a function 
of drain current; typical values Fig 10. Normalized drain-source on-state resistance 
factor as a function of junction temperature
Fig 11. Gate-source voltage as a function of gate 
charge; typical values
Fig 12. Input, output and reverse transfer capacitances 
as a function of drain-source voltage; typical 
values
03ag21
0
5
10
15
20
25
0 2 04 06 08 0
ID (A)
RDSon
(mΩ)
VGS = 4.5 V
Tj = 25 °C
5V
10 V
6 V
03af18
0
0.5
1
1.5
2
-60 0 60 120 180
Tj (°C)
a
03ag25
0
2
4
6
8
10
0 1 02 03 0
QG (nC)
VGS
(V)
Tj = 25 °C
ID = 50 A
VDD = 15 V
03ag24
  10
2
  10
3
  10
4
10
-1    1   10  10
2
VDS (V)
C 
(pF)
Ciss
Coss
CrssPHB66NQ03LT_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 30 January 2009 9 of 13
NXP Semiconductors PHB66NQ03LT
N-channel TrenchMOS logic level FET
Fig 13. Source current as a function of source-drain voltage; typical values
03ag23
0
20
40
60
80
0 0.3 0.6 0.9 1.2
VSD (V)
IS
(A)
Tj = 25 °C 175 °C
VGS = 0 VPHB66NQ03LT_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 30 January 2009 10 of 13
NXP Semiconductors PHB66NQ03LT
N-channel TrenchMOS logic level FET
7. Package outline
 
Fig 14. Package outline SOT404 (D2PAK)
UNIT A
 REFERENCES OUTLINE
VERSION
EUROPEAN
PROJECTION ISSUE DATE
 IEC  JEDEC  JEITA
mm
A1 D1
D
max.
E eL p HD Q c
2.54 2.60
2.20
15.80
14.80
2.90
2.10
11 1.60
1.20
10.30
9.70
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
b
DIMENSIONS (mm are the original dimensions)
 SOT404
0 2.5 5 mm
scale
Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped) SOT404
e e
E
b
D1
HD
D
Q
Lp
c
A1
A
13
2
mounting
base
05-02-11
06-03-16PHB66NQ03LT_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 30 January 2009 11 of 13
NXP Semiconductors PHB66NQ03LT
N-channel TrenchMOS logic level FET
8. Revision history
 
Table 7. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PHB66NQ03LT_7 20090130 Product data sheet - PHB_PHD66NQ03LT_6
Modifications: • The format of this data sheet has been redesigned to comply with the new identity 
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
PHB_PHD66NQ03LT_6
(9397 750 13429)
20040802 Product data sheet - PHP_PHB_PHD66NQ03LT_5
PHP_PHB_PHD66NQ03LT_5
(9397 750 13107)
20040415 Product data sheet - PHP_PHB_PHD66NQ03LT_4
PHP_PHB_PHD66NQ03LT_4
(9397 750 10158)
20020909 Product data sheet - PHP_PHB_PHD66NQ03LT_3
PHP_PHB_PHD66NQ03LT_3
(9397 750 09284)
20020312 Product data sheet - PHP_PHB_PHD66NQ03LT_2
PHP_PHB_PHD66NQ03LT_2
(9397 750 09119)
20011210 Product data sheet - PHP_PHB_PHD66NQ03LT_1
PHP_PHB_PHD66NQ03LT_1
(9397 750 08725)
20011012 Product data sheet - -PHB66NQ03LT_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 30 January 2009 12 of 13
NXP Semiconductors PHB66NQ03LT
N-channel TrenchMOS logic level FET
9. Legal information
9.1 Data sheet status
 
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product 
status information is available on the Internet at URL http://www.nxp.com.
9.2 Definitions
Draft — The document is a draft version only. The content is still under 
internal review and subject to formal approval, which may result in 
modifications or additions. NXP Semiconductors does not give any 
representations or warranties as to the accuracy or completeness of 
information included herein and shall have no liability for the consequences of 
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet 
with the same product type number(s) and title. A short data sheet is intended 
for quick reference only and should not be relied upon to contain detailed and 
full information. For detailed and full information see the relevant full data 
sheet, which is available on request via the local NXP Semiconductors sales 
office. In case of any inconsistency or conflict with the short data sheet, the 
full data sheet shall prevail.
9.3 Disclaimers
General — Information in this document is believed to be accurate and 
reliable. However, NXP Semiconductors does not give any representations or 
warranties, expressed or implied, as to the accuracy or completeness of such 
information and shall have no liability for the consequences of use of such 
information.
Right to make changes — NXP Semiconductors reserves the right to make 
changes to information published in this document, including without 
limitation specifications and product descriptions, at any time and without 
notice. This document supersedes and replaces all information supplied prior 
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed, 
authorized or warranted to be suitable for use in medical, military, aircraft, 
space or life support equipment, nor in applications where failure or 
malfunction of an NXP Semiconductors product can reasonably be expected 
to result in personal injury, death or severe property or environmental 
damage. NXP Semiconductors accepts no liability for inclusion and/or use of 
NXP Semiconductors products in such equipment or applications and 
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these 
products are for illustrative purposes only. NXP Semiconductors makes no 
representation or warranty that such applications will be suitable for the 
specified use without further testing or modification.
Quick reference data — The Quick reference data is an extract of the 
product data given in the Limiting values and Characteristics sections of this 
document, and as such is not complete, exhaustive or legally binding. 
Limiting values — Stress above one or more limiting values (as defined in 
the Absolute Maximum Ratings System of IEC 60134) may cause permanent 
damage to the device. Limiting values are stress ratings only and operation of 
the device at these or any other conditions above those given in the 
Characteristics sections of this document is not implied. Exposure to limiting 
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold 
subject to the general terms and conditions of commercial sale, as published 
at http://www.nxp.com/profile/terms, including those pertaining to warranty, 
intellectual property rights infringement and limitation of liability, unless 
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of 
any inconsistency or conflict between information in this document and such 
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted or 
construed as an offer to sell products that is open for acceptance or the grant, 
conveyance or implication of any license under any copyrights, patents or 
other industrial or intellectual property rights.
9.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks 
are the property of their respective owners.
TrenchMOS — is a trademark of NXP B.V.
10. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status [1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.NXP Semiconductors PHB66NQ03LT
N-channel TrenchMOS logic level FET
© NXP B.V. 2009. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 30 January 2009
Document identifier: PHB66NQ03LT_7
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’. 
11. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1 General description  . . . . . . . . . . . . . . . . . . . . . .1
1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . .1
1.3 Applications  . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.4 Quick reference data  . . . . . . . . . . . . . . . . . . . . .1
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . .2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . .2
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3
5 Thermal characteristics  . . . . . . . . . . . . . . . . . . .5
6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .6
7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10
8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . .11
9 Legal information. . . . . . . . . . . . . . . . . . . . . . . .12
9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12
9.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
9.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .12
9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12
10 Contact information. . . . . . . . . . . . . . . . . . . . . .12

Dynamic characteristics

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Dynamic characteristics

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